M16C6NK Datasheet, PDF (179/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
Table 15.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table
15.3 shows pin functions for the case where the multiple transfer clock output pin select function is
deselected. Table 15.4 lists the P6_4 pin functions during clock synchronous serial I/O mode.
Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TXDi
pin outputs an “H”.
Figure 15.11 shows the transmit/receive timings during clock synchronous serial I/O mode.
Table 15.3 Pin Functions (When Not Select Multiple Transfer Clock Output Pin Function)
Pin Name
Function
Method of Selection
TXDi
Serial Data Output (Outputs dummy data when performing reception only)
(P6_3, P6_7, P7_0)
RXDi
Serial Data Input PD6_2 and PD6_6 bits in PD6 register = 0
(P6_2, P6_6, P7_1)
PD7_1 bit in PD7 register = 0
(Can be used as an input port when performing transmission only)
CLKi
Transfer Clock Output CKDIR bit in UiMR register = 0
(P6_1, P6_5, P7_2) Transfer Clock Input CKDIR bit = 1
PD6_1 and PD6_5 bits in PD6 register = 0
_________ ________
CTSi/RTSi
________
CTS Input
PD7_2 bit in PD7 register = 0
CRD bit in UiC0 register = 0
(P6_0, P6_4, P7_3)
CRS bit in UiC0 register = 0
PD6_0 and PD6_4 bits in PD6 register = 0
________
RTS Output
PD7_3 bit in PD7 register = 0
CRD bit = 0
CRS bit = 1
I/O Port
CRD bit = 1
i = 0 to 2
Table 15.4 P6_4 Pin Functions
Bit set Value
Pin Function
U1C0 Register
UCON Register
PD6 Register
CRD bit CRS bit RCSP bit CLKMD1 bit CLKMD0 bit
PD6_4 bit
P6_4
_________
CTS1
_________
RTS1
_________
CTS0 ⁽¹⁾
1
-
0
0
-
Input: 0, Output: 1
0
0
0
0
-
0
0
1
0
0
-
-
0
0
1
0
-
0
CLKS1
-
-
-
1 ⁽²⁾
1
-
-: “0” or “1”
NOTES:
__________ __________
1. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS
__________
bit in the U0C0 register to “1” (RTS0 selected).
2. When the CLKMD1 bit = 1 and the CLKMD0 bit = 0, the following logic levels are output:
• High if the CLKPOL bit in the U1C0 register = 0
• Low if the CLKPOL bit = 1
Rev.2.00 Nov 28, 2005 page 161 of 378
REJ09B0124-0200