M16C6NK Datasheet, PDF (71/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
7. Bus
Table 7.8 Software Wait Related Bits and Bus Cycles
Area
Bus
Mode
PM2 Register
PM20 Bit
PM1 Register
PM17 Bit ⁽⁵⁾
CSR Register
CS3W Bit ⁽¹⁾
CS2W Bit ⁽¹⁾
CS1W Bit ⁽¹⁾
CS0W Bit ⁽¹⁾
CSE Register
CS31W
CS21W
to
to
CS30W
CS20W
Bits
Bits
Software
CS11W to CS10W Bits ^Wait
CS01W to CS00W Bits
Bus Cycle
SFR
-
0
-
-
-
- 3 BCLK cycles ⁽⁴⁾
-
1
-
-
-
- 2 BCLK cycles ⁽⁴⁾
Internal -
-
0
-
-
No wait 1 BCLK cycle ⁽³⁾
ROM, RAM -
-
1
-
-
1 wait 2 BCLK cycles
External Separate -
0
1
00b
No wait 1 BCLK cycle (read)
Area Bus
2 BCLK cycles (write)
-
-
0
00b
1 wait 2 BCLK cycles ⁽³⁾
-
-
0
01b
2 waits 3 BCLK cycles
-
-
0
10b
3 waits 4 BCLK cycles
-
1
0
00b
1 wait 2 BCLK cycles
Multiplexed -
-
0
00b
1 wait 3 BCLK cycles
Bus ⁽²⁾
-
-
0
01b
2 waits 3 BCLK cycles
-
-
0
10b
3 waits 4 BCLK cycles
-
1
0
00b
1 wait 3 BCLK cycles
NOTES:
________
1. To use the RDY signal, set this bit to “0 ”.
2. To access in multiplexed bus mode, set the corresponding bit of CS0W to CS3W to “0” (with wait state).
3. After reset, the PM17 bit is set to “0” (without wait state), all of the CS0W to CS3W bits are set to “0”
_______
_______
(with wait state), and the CSE register is set to “00h” (one wait state for CS0 to CS3). Therefore, the
internal RAM and internal ROM are accessed with no wait state, and all external areas are accessed
with one wait state.
4. When the selected CPU clock source is the PLL clock, the number of wait cycles can be altered by the
PM20 bit in the PM2 register. When using PLL clock over 16 MHz, be sure to set the PM20 bit to “0”
(2 wait cycles).
5. When the PM17 bit is set to “1” and access an external area, set the CSiW bits (i = 0 to 3) to “0” (with
wait sate).
Rev.2.00 Nov 28, 2005 page 53 of 378
REJ09B0124-0200