M16C6NK Datasheet, PDF (70/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
7. Bus
7.2.9 External Bus Status When Internal Area Accessed
Table 7.7 shows the external bus status when the internal area is accessed.
Table 7.7 External Bus Status When Internal Area Accessed
Item
SFR Accessed
Internal ROM, Internal RAM Accessed
A0 to A19
Address output
Maintain status before accessed address
of external area or SFR
D0 to D15 When read High-impedance
High-impedance
When write
_____ ______ ________ _________
RD, WR, WRL, WRH
________
BHE
Output data
_____ ______ _________ __________
RD, WR, WRL, WRH output
________
BHE output
Undefined
Output “H”
Maintain status before accessed status of
_______
_______
CS0 to CS3
Output “H”
external area or SFR
Output “H”
ALE
Output “L”
Output “L”
7.2.10 Software Wait
Software wait states can be inserted by using the PM17 bit in the PM1 register, the CS0W to CS3W bits
in the CSR register, and the CSE register. The SFR area is unaffected by these control bits. This area is
always accessed in 2 BCLK or 3 BCLK cycles as determined by the PM20 bit in the PM2 register. See
Table 7.8 Bit and Bus Cycle Related to Software Wait for details.
________
To use the RDY signal, set the corresponding CS3W to CS0W bit to “0” (with wait state). Figure 7.6 shows
the CSE register. Table 7.8 shows the software wait related bits and bus cycles. Figures 7.7 and 7.8 show
the typical bus timings using software wait.
Chip Select Expansion Control Register ⁽²⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CSE
Address
001Bh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
CSE00W
b1 b0
0 0 : 1 wait
RW
CS0 Wait Expansion Bit ^{(1) 0 1 : 2 waits}
CSE01W
1 0 : 3 waits
1 1 : Do not set a value
RW
CSE10W
b3 b2
0 0 : 1 wait
RW
CS1 Wait Expansion Bit ^{(1) 0 1 : 2 waits}
1 0 : 3 waits
CSE11W
1 1 : Do not set a value
RW
CS20WE
b5 b4
0 0 : 1 wait
RW
CS2 Wait Expansion Bit ^{(1) 0 1 : 2 waits}
CSE21W
1 0 : 3 waits
1 1 : Do not set a value
RW
b7 b6
CSE30W
0 0 : 1 wait
RW
CS3 Wait Expansion Bit ^{(1) 0 1 : 2 waits}
1 0 : 3 waits
CSE31W
1 1 : Do not set a value
RW
NOTES:
1. Set the CSiW bit (i = 0 to 3) in the CSR register to "0" (with wait state) before writing to the CSEi1W to CSEi0W
bits. If the CSiW bit needs to be set to "1" (without wait state), set the CSEi1W to CSEi0W bits to "00b" before
setting it.
2. Not available this register in T/V-ver..
Figure 7.6 CSE Register
Rev.2.00 Nov 28, 2005 page 52 of 378
REJ09B0124-0200