M16C6NK Datasheet, PDF (112/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
10. Interrupt
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10.6 INT Interrupt
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INTi interrupt (i = 0 to 8) ⁽¹⁾ is triggered by the edges of external inputs. The edge polarity is selected using
the IFSR10 to IFSR15 bits in the IFSR1 register and the IFSR23 to IFSR25 bits in the IFSR2 register.
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INT4 share the interrupt vector and interrupt control register with CAN1 successful transmission and SI/O3,
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INT5 share with CAN1 successful reception and SI/O4, INT6 share with Timer A3, INT7 share with Timer
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A2, INT8 share with Timer B1. To use the INT4 to INT8 interrupts ⁽¹⁾, set the each bits as follows.
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• To use the INT4 interrupt: Set the IFSR16 bit in the IFSR1 register to “1” (INT4).
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• To use the INT5 interrupt: Set the IFSR17 bit in the IFSR1 register to “1” (INT5).
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• To use the INT6 interrupt: Set the IFSR21 bit in the IFSR2 register to “1” (INT6). ⁽¹⁾
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• To use the INT7 interrupt: Set the IFSR20 bit in the IFSR2 register to “1” (INT7). ⁽¹⁾
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• To use the INT8 interrupt: Set the IFSR22 bit in the IFSR2 register to “1” (INT8). ⁽¹⁾
After modifying the IFSR16, IFSR17, IFSR20, IFSR21 and IFSR22 bits, set the corresponding IR bit to “0”
(interrupt not requested) before enabling the interrupt.
NOTE:
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1. INT6 to INT8 interrupts are only in the 128-pin version.
Figures 10.11 to 10.13 show the IFSR0, IFSR1 and IFSR2 registers.
Rev.2.00 Nov 28, 2005 page 94 of 378
REJ09B0124-0200