M16C6NK Datasheet, PDF (148/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
13. Timers
13.2 Timer B
Figure 13.15 shows a block diagram of the timer B. Figures 13.16 and 13.17 show the timer B-related
registers.
Timer B supports the following three modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0
to 5) to select the desired mode.
• Timer mode
: The timer counts an internal count source.
• Event counter mode
: The timer counts pulses from an external device or over
flows or underflows of other timers.
• Pulse period/pulse width measuring mode : The timer measures pulse period or pulse width of an
external signal.
Select clock source
f1 or f2
f8
f32
fC32
TCK1 to TCK0
00
01
10
11
TBj overflow ⁽¹⁾
TBiIN
Polarity Switching
and Edge Pulse
00: Timer
10: Pulse period measurement mode,
pulse width measurement mode
TCK1
1
0
01: Event counter
TMOD1 to TMOD0
TBiS
High-order Bits of Data Bus
Low-order Bits of Data Bus
Low-order
8 bits
Reload Register
High-order
8 bits
Counter
Counter Reset Circuit
TCK1 to TCK0, TMOD1 to TMOD0: Bits in TBiMR register
TBiS: Bit in TABSR register or TBSR register
i = 0 to 5
j = i - 1 except j = 2 when i = 0, j = 5 when i = 3
NOTE:
1. Overflow or underflow
TBi
Timer B0
Timer B1
Timer B2
Timer B3
Timer B4
Timer B5
Addresses
0391h - 0390h
0393h - 0392h
0395h- 0394h
01D1h- 01D0h
01D3h- 01D2h
01D5h- 01D4h
TBj
Timer B2
Timer B0
Timer B1
Timer B5
Timer B3
Timer B4
Figure 13.15 Timer B Block Diagram
Rev.2.00 Nov 28, 2005 page 130 of 378
REJ09B0124-0200