M16C6NK Datasheet, PDF (168/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
Main clock, PLL clock, or on-chip oscillator clock
1/2 ^f2SIO
f1SIO
0 ^PCLK1
1
f1SIO or f2SIO
1/8
f8SIO
(UART0)
1/4
f32SIO
RXD0
RXD polarity
reversing circuit
Clock source selection
CLK1 to CLK0
f1SIO or f2SIO ^00h
f8SIO ^01h
f32SIO ^10h
CKDIR
Internal
0
1
External
U0BRG
register
1 / (n0+1)
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16
Clock synchronous
type
001
Reception
control circuit
Receive
clock
UART transmission
1/16 _{010, 100, 101, 110}
Clock synchronous type
001
Transmission
control circuit
Clock synchronous type
(when internal clock is selected)
1/2
0
Transmit
clock
Transmit/
receive
unit
CLK0
CTS0 /
RTS0
1
CKPOL
CLK
polarity
reversing
circuit
Clock synchronous type
(when internal clock is selected)
Clock synchronous
type
CKDIR
(when external clock
is selected)
CTS/RTS disabled
CTS/RTS selected
1
CRS 0
RCSP
0
VSS
1
RTS0
CTS/RTS disabled
CTS0
1
CTS0 from UART1
0
CRD
n0: Values set to the U0BRG register
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U0MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U0C0 register
RCSP: Bit in UCON register
TXD
polarity
reversing
circuit
TXD0
Figure 15.1 UART0 Block Diagram
Main clock, PLL clock, or on-chip oscillator clock
11//22 ^f2SIO
f1SIO
0 ^PCLK1
1
f1SIO or f2SIO
1/8
f8SIO
(UART1)
1/4
f32SIO
RXD1
RXD polarity reversing
circuit
Clock source selection
CLK1 to CLK0 _CKDIR
f1SIO or f2SIO ⁰⁰
Internal
f8SIO ⁰¹
0
f32SIO ¹⁰
1
External
U1BRG
register
1 / (n1+1)
UART reception SMD2 to SMD0
010, 100, 101, 110
1/16
Clock synchronous
type
001
Reception
control circuit
UART transmission
010, 100, 101, 110
1/16
Clock synchronous
type
001
Transmission
control circuit
Receive
clock
Transmit
clock
Clock synchronous type
(when internal clock is selected)
1/2
0
Clock synchronous type
(when external clock is selected))
1
CLK1
CTS1 / RTS1/
CTS0 / CLKS1
CKPOL
CLK
polarity
reversing
circuit
Clock output
pin select
CLKMD0
0
Clock synchronous type
(when internal clock is selected)
1
1 CTS/RTS selected _{CTS/RTS disabled}
CRS ₁
0
CLKMD1
VSS
0
1 CTS/RTS disabled
CKDIR
RTS1
0 CTS1
n1: Values set to the U1BRG register
0
CRD
1
RCSP
CTS0 from UART0
PCLK1: Bit in PCLKR register
SMD2 to SMD0, CKDIR: Bits in U1MR register
CLK1 to CLK0, CKPOL, CRD, CRS: Bits in U1C0 register
CLKMD0, CLKMD1, RCSP: Bits in UCON register
Transmit/
receive
unit
TXD
polarity
reversing
circuit
TXD1
Figure 15.2 UART1 Block Diagram
Rev.2.00 Nov 28, 2005 page 150 of 378
REJ09B0124-0200