M16C6NK Datasheet, PDF (159/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
14. Three-Phase Motor Control Timer Function
Three-Phase PWM Control Register 1⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
0
Symbol
INVC1
Address
01C9h
After Reset
00h
Bit
Symbol
Bit Name
Function
RW
Timer A1, A2 and A4
INV10 _{Start Trigger Select Bit}
0: Timer B2 underflow
1: Timer B2 underflow and write to
the timer B2
RW
INV11
Timer A1-1, A2-1, A4-1
Control Bit ⁽²⁾
0: Three-phase mode 0 ⁽³⁾
1: Three-phase mode 1
RW
INV12
Dead Time Timer
0 : f1 or f2
Count Source Select Bit 1 : f1 divided-by-2 or f2 divided-by-2
RW
INV13
Carrier Wave Detect
Flag ⁽⁴⁾
0: Timer A1 reload control signal is "0"
1: Timer A1 reload control signal is "1"
RO
INV14
Output Polarity Control
Bit
0 : Active "L" of an output waveform
1 : Active "H" of an output waveform
RW
INV15 Dead Time Disable Bit
Dead Time Timer
INV16 _{Trigger Select Bit}
-
(b7) ^{Reserved Bit}
0: Enables dead time
1: Disables dead time
RW
0: Falling edge of a one-shot pulse of
the timer A1, A2, A4 ⁽⁵⁾
1: Rising edge of the three-phase output ^RW
shift register (U-, V-, W-phase)
Set to "0"
RW
NOTES:
1. Rewrite the INVC1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).
The timers A1, A2, A4, and B2 must be stopped during rewrite.
2. The following table lists how the INV11 bit works.
Item
INV11 = 0
INV11 = 1
Mode
Three-phase mode 0
Three-phase mode 1
TA11, TA21 and TA41 Registers Not used
Used
INV00 and INV01 Bit
Disabled. The ICTB2 counter is
incremented whenever the timer B2 Enabled
underflows
INV13 Bit
Disabled
Enabled when INV11=1 and INV06=0
3. When the INV06 bit is set to "1" (sawtooth wave modulation mode), set the INV11 bit to "0" (three-phase
mode 0). Also, when the INV11 bit is set to "0", set the PWCON bit in the TB2SC register to "0" (timer B2
is reloaded when the timer B2 underflows).
4. The INV13 bit is enabled only when the INV06 bit is set to "0" (Triangular wave modulation mode) and the
INV11 bit to "1" (three-phase mode 1).
5. If the following conditions are all met, set the INV16 bit to "1" (rising edge of the three-phase output shift
register).
The INV15 bit is set to "0" (dead time timer enabled)
The Dij bit (i=U, V or W, j=0, 1) and DiBj bit always have different values when the INV03 bit
is set to "1". (The positive-phase and negative-phase always output opposite level signals.)
If above conditions are not met, set the INV16 bit to "0" (falling edge of a one-shot pulse of the timer A1,
A2, A4).
Figure 14.3 INVC1 Register
Rev.2.00 Nov 28, 2005 page 141 of 378
REJ09B0124-0200