M16C6NK Datasheet, PDF (125/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
12. DMAC
DMAi Source Pointer (i = 0, 1) ⁽¹⁾
(b23)
(b19)
(b16)(b15)
(b8)
b7
b3
b0 b7
b0 b7
b0
Function
Set the source address of transfer
Symbol
SAR0
SAR1
Address
0022h to 0020h
0032h to 0030h
After Reset
Indeterminate
Indeterminate
Setting Range RW
00000h to FFFFFh RW
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
NOTE:
1. If the DSD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0" (DMA disabled).
If the DSD bit is "1" (forward direction), this register can be written to at any time.
If the DSD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Destination Pointer (i = 0, 1) ⁽¹⁾
(b23)
b7
(b19)
b3
(b16)(b15)
b0 b7
(b8)
b0 b7
b0 Symbol
DAR0
DAR1
Address
0026h to 0024h
0036h to 0034h
After Reset
Indeterminate
Indeterminate
Function
Setting Range RW
Set the destination address of transfer
00000h to FFFFFh RW
Nothing is assigned. When write, set to "0".
When read, their contents are "0".
-
NOTE:
1. If the DAD bit in the DMiCON register is "0" (fixed), this register can only be written to when the DMAE bit in the
DMiCON register is "0" (DMA disabled).
If the DAD bit is "1" (forward direction), this register can be written to at any time.
If the DAD bit is "1" and the DMAE bit is "1" (DMA enabled), the DMAi forward address pointer can be read from
this register. Otherwise, the value written to it can be read.
DMAi Transfer Counter (i = 0, 1)
(b15)
b7
(b8)
b0 b7
b0
Symbol
Address
After Reset
TCR0 0029h, 0028h Indeterminate
TCR1 0039h, 0038h Indeterminate
Function
Setting Range RW
Set the transfer count minus 1.
The written value is stored in the DMAi transfer counter
reload register, and when the DMAE bit in the DMiCON
register is set to "1" (DMA enabled) or the DMAi transfer
counter underflows when the DMASL bit in the DMiCON 0000h to FFFFh
RW
register is "1" (repeat transfer), the value of the DMAi
transfer counter reload register is transferred to the DMAi
transfer counter.
When read, the DMAi transfer counter is read.
Figure 12.4 SAR0 and SAR1 Registers, DAR0 and DAR1 Registers, TCR0 and TCR1 Registers
Rev.2.00 Nov 28, 2005 page 107 of 378
REJ09B0124-0200