M16C6NK Datasheet, PDF (154/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
13. Timers
Timer Bi Mode Register (i = 0 to 5)
b7 b6 b5 b4 b3 b2 b1 b0
10
Symbol
TB0MR to TB2MR
TB3MR to TB5MR
Address
039Bh to 039Dh
01DBh to 01DDh
After Reset
00XX0000b
00XX0000b
Bit Symbol
Bit Name
Function
RW
TMOD0 _{Operation Mode}
b1 b0
1 0 : Pulse period / pulse width
RW
TMOD1 ^{Select Bit}
measurement mode
RW
b3 b2
0 0 : Pulse period measurement
MR0
(Measurement between a falling edge and the
next falling edge of measured pulse)
RW
0 1 : Pulse period measurement
Measurement Mode
(Measurement between a rising edge and the next
Select Bit
rising edge of measured pulse)
1 0 : Pulse width measurement
MR1
(Measurement between a falling edge and the
next rising edge of measured pulse and between
RW
a rising edge and the next falling edge)
1 1 : Do not set a value
TB0MR and TB3MR registers
Set to "0" in pulse period and pulse width measurement mode
RW
MR2
TB1MR, TB2MR, TB4MR, TB5MR registers
Nothing is assigned. When write, set to "0".
-
When read, its content turns out to be indeterminate.
MR3
Timer Bi Overflow
Flag ⁽¹⁾
0 : Timer did not overflow
1 : Timer has overflown
RO
b7 b6
TCK0
TCK1
Count Source
Select Bit
0 0 : f1 or f2
0 1 : f8
1 0 : f32
1 1 : fC32
RW
RW
NOTE:
1. This flag is indeterminate after reset. When the TBiS bit = 1 (start counting), the MR3 bit is set to "0" (no overflow) by writing to the
TBiMR register at the next count timing or later after the MR3 bit was set to "1" (overflow). The MR3 bit cannot be set to "1" in a
program. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register, and the TB3S to TB5S bits are assigned
to the bit 5 to bit 7 in the TBSR register.
Figure 13.20 TB0MR to TB5MR Registers in Pulse Period and Pulse Width Measurement Mode
Rev.2.00 Nov 28, 2005 page 136 of 378
REJ09B0124-0200