M16C6NK Datasheet, PDF (157/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
14. Three-Phase Motor Control Timer Function
INV00 to INV07: Bits in INVC0 register
INV10 to INV15: Bits in INVC1 register
DUi, DUBi: Bits in IDBi register (i = 0, 1)
TA1S to TA4S: Bits in TABSR register
PWCON: Bits in TB2SC register
INV13
ICTB2 Register n=1 to 15
INV03
Value to be written to
INV03 bit
DQ
INV00
Reload Control Signal for Timer A1
INV01
INV11
Circuit to set Interrupt
Generation Frequency
1
0
PWCON
ICTB2 Counter
n=1 to 15
Write signal to INV03 bit T
RESET
Timer B2
NMI
Interrupt _INV05
Request Bit
R
INV02
Timer B2 Underflow
Timer B2
(Timer Mode)
f1 or f2 1/2
INV07
0
1
INV12
INV06
Reload Register
n = 1 to 255
Trigger
Write signal to
Timer B2
INV10
Transfer Trigger ⁽¹⁾
Dead Time
Trigger
Timer
DQ
n = 1 to 255
T
Start Trigger Signal for Timers A1, A2, A4
U-phase Output
Control Circuit
INV04
INV14
Inverse
Control
U
TA4 Register TA41 Register
Reload
Reload Control
Signal for Timer A4
Trigger
Timer A4 Counter
(One-Shot Timer Mode)
INV11
TQ
Timer A4
One-Shot
Pulse
When setting the TA4S bit to "0",
signal is set to "0"
DU1 DU0
bit
bit
DQ DQ
T
T
DUB1 DUB0
bit
bit
DQ DQ
T
T
U-Phase
Output Signal
Three-Phase
Output
Shift Register
(U Phase)
DQ
U-Phase
T
Output Signal
Inverse
Control
U
TA1 Register TA11 Register
Reload
Reload Control
Signal for Timer A1
Trigger
Timer A1 Counter
(One-Shot Timer Mode)
INV11
TQ
Timer A1
One-Shot
Pulse
When setting the TA1S bit to "0",
signal is set to "0"
TA2 Register TA21 Register
Reload
Reload Control
Signal for Timer A2
Trigger
Timer A2 Counter
(One-Shot Timer Mode)
INV11
TQ
Timer A2
One-Shot
Pulse
When setting the TA2S bit to "0",
signal is set to "0"
INV06
Trigger
Trigger
Dead Time
Timer
n = 1 to 255
V-Phase Output
Control Circuit
DQ
V-Phase
T
Output Signal
DQ
V-Phase
T
Output Signal
INV06
Trigger
Trigger
Dead Time
Timer
n = 1 to 255
W-Phase Output
Control Circuit
DQ
W-Phase
T
Output Signal
DQ
W-Phase
T
Output Signal
Inverse
V
Control
Inverse
Control
V
Inverse
Control
W
Inverse
Control
W
Switching to P8_0, P8_1 and P7_2 to P7_5 is not shown in this diagram.
NOTE:
1. Transfer trigger is generated only when the IDB0 and IDB1 registers are set and the first timer B2 underflows,
if the INV06 bit is set to "0" (triangular wave modulation mode).
Figure 14.1 Three-Phase Motor Control Timer Function Block Diagram
Rev.2.00 Nov 28, 2005 page 139 of 378
REJ09B0124-0200