M16C6NK Datasheet, PDF (381/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
23. Usage Precaution
fCAN
CPU read signal
Updating period of
CAN module
CPU reset signal
CiSTR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
i = 0, 1
✕
✕
✕
✕
✕
✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read
period, it does not enter reset mode, for the CPU read has the higher priority.
Figure 23.5 When Updating Period of CAN Module Matches Access Period from CPU
CPU read signal
Updating period of
the CAN module
CPU reset signal
CiSTR register
b8: Reset state flag
0: CAN operation
mode
1: CAN reset/initial-
ization mode
i = 0, 1
Wait time
: Updated without fail in period of 3fCAN
Figure 23.6 With a Wait Time of 3fCAN Before CPU Read
CPU read signal
Updating period of
the CAN module
CPU reset signal
CiSTR register
b8: State_Reset bit
0: CAN operation
mode
1: CAN reset/initial-
ization mode
i = 0, 1
4fCAN
✕
✕: When the CAN module’s State_Reset bit updating period matches the CPU’s read
period, it does not enter reset mode, for the CPU read has the higher priority.
: Updated without fail in period of 4fCAN
Figure 23.7 When Polling Period of CPU is 3fCAN or Longer
Rev.2.00 Nov 28, 2005 page 363 of 378
REJ09B0124-0200