M16C6NK Datasheet, PDF (337/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
22. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3V
(Referenced to VCC = 3.3V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 22.45 Memory Expansion Mode and Microprocessor Mode
(for 2- to 3-wait setting, external area access and multiplexed bus selection)
Symbol
Parameter
Measuring
condition
Standard
Min.
Max.
Unit
td(BCLK-AD) Address output delay time
Figure 22.12
50
ns
th(BCLK-AD) Address output hold time (refers to BCLK)
4
ns
th(RD-AD) Address output hold time (refers to RD)
(NOTE 1)
ns
th(WR-AD) Address output hold time (refers to WR)
(NOTE 1)
ns
td(BCLK-CS) Chip select output delay time
50
ns
th(BCLK-CS) Chip select output hold time (refers to BCLK)
4
ns
th(RD-CS) Chip select output hold time (refers to RD)
(NOTE 1)
ns
th(WR-CS) Chip select output hold time (refers to WR)
(NOTE 1)
ns
td(BCLK-RD) RD signal output delay time
40
ns
th(BCLK-RD) RD signal output hold time
0
ns
td(BCLK-WR) WR signal output delay time
40
ns
th(BCLK-WR) WR signal output hold time
0
ns
td(BCLK-DB) Data output delay time (refers to BCLK)
50
ns
th(BCLK-DB) Data output hold time (refers to BCLK)
4
ns
td(DB-WR) Data output delay time (refers to WR)
(NOTE 2)
ns
th(WR-DB) Data output hold time (refers to WR)
__________
td(BCLK-HLDA) HLDA output delay time
(NOTE 1)
ns
40
ns
td(BCLK-ALE) ALE signal output delay time (refers to BCLK)
25
ns
th(BCLK-ALE) ALE signal output hold time (refers to BCLK)
–4
ns
td(AD-ALE) ALE signal output delay time (refers to Address)
(NOTE 3)
ns
th(ALE-AD) ALE signal output hold time (refers to Address)
(NOTE 4)
ns
td(AD-RD) RD signal output delay from the end of Address
0
ns
td(AD-WR) WR signal output delay from the end of Address
0
ns
tdZ(RD-AD) Address output floating start time
8
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 10 [ns]}
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
(n –0.5) ✕ 10⁹
– 50 [ns]
f(BCLK)
n is “2” for 2-wait setting, “3” for 3-wait setting.
3. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 40 [ns]}
f(BCLK)
4. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 15 [ns]}
f(BCLK)
Rev.2.00 Nov 28, 2005 page 319 of 378
REJ09B0124-0200