M16C6NK Datasheet, PDF (44/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
4. Special Function Register (SFR)
Table 4.8 SFR Information (8)
Address
Register
01C0h
01C1h
01C2h
01C3h
01C4h
01C5h
01C6h
01C7h
01C8h
01C9h
01CAh
01CBh
01CCh
01CDh
01CEh
01CFh
01D0h
01D1h
01D2h
01D3h
01D4h
01D5h
01D6h
01D7h
01D8h
01D9h
01DAh
01DBh
01DCh
01DDh
01DEh
01DFh
01E0h
01E1h
01E2h
01E3h
01E4h
01E5h
01E6h
01E7h
01E8h
01E9h
01EAh
01EBh
01ECh
01EDh
01EEh
01EFh
01F0h
01F1h
01F2h
01F3h
01F4h
01F5h
01F6h
01F7h
01F8h
01F9h
01FAh
01FBh
01FCh
01FDh
01FEh
01FFh
Timer B3, B4, B5 Count Start Flag
Timer A1-1 Register
Timer A2-1 Register
Timer A4-1 Register
Three-Phase PWM Control Register 0
Three-Phase PWM Control Register 1
Three-Phase Output Buffer Register 0
Three-Phase Output Buffer Register 1
Dead Time Timer
Timer B2 Interrupt Occurrence Frequency Set Counter
Interrupt Cause Select Register 2
Timer B3 Register
Timer B4 Register
Timer B5 Register
SI/O6 Transmit/Receive Register ⁽¹⁾
SI/O6 Control Register ⁽¹⁾
SI/O6 Bit Rate Generator ⁽¹⁾
SI/O3, 4, 5, 6 Transmit/Receive Register ⁽²⁾
Timer B3 Mode Register
Timer B4 Mode Register
Timer B5 Mode Register
Interrupt Cause Select Register 0
Interrupt Cause Select Register 1
SI/O3 Transmit/Receive Register
SI/O3 Control Register
SI/O3 Bit Rate Generator
SI/O4 Transmit/Receive Register
SI/O4 Control Register
SI/O4 Bit Rate Generator
SI/O5 Transmit/Receive Register ⁽¹⁾
SI/O5 Control Register ⁽¹⁾
SI/O5 Bit Rate Generator ⁽¹⁾
UART0 Special Mode Register 4
UART0 Special Mode Register 3
UART0 Special Mode Register 2
UART0 Special Mode Register
UART1 Special Mode Register 4
UART1 Special Mode Register 3
UART1 Special Mode Register 2
UART1 Special Mode Register
UART2 Special Mode Register 4
UART2 Special Mode Register 3
UART2 Special Mode Register 2
UART2 Special Mode Register
UART2 Transmit/Receive Mode Register
UART2 Bit Rate Generator
UART2 Transmit Buffer Register
UART2 Transmit/Receive Control Register 0
UART2 Transmit/Receive Control Register 1
UART2 Receive Buffer Register
X: Undefined
Symbol
TBSR
TA11
TA21
TA41
INVC0
INVC1
IDB0
IDB1
DTT
ICTB2
IFSR2
TB3
TB4
TB5
S6TRR
S6C
S6BRG
S3456TRR
TB3MR
TB4MR
TB5MR
IFSR0
IFSR1
S3TRR
S3C
S3BRG
S4TRR
S4C
S4BRG
S5TRR
S5C
S5BRG
U0SMR4
U0SMR3
U0SMR2
U0SMR
U1SMR4
U1SMR3
U1SMR2
U1SMR
U2SMR4
U2SMR3
U2SMR2
U2SMR
U2MR
U2BRG
U2TB
U2C0
U2C1
U2RB
NOTES:
1. These registers exist only in the 128-pin version.
2. The S5TRF and S6TRF bits in the S3456TRR register are used in the 128-pin version.
3. The blank areas are reserved and cannot be accessed by users.
After Reset
000XXXXXb
XXh
XXh
XXh
XXh
XXh
XXh
00h
00h
00h
00h
XXh
XXh
X0000000b
XXh
XXh
XXh
XXh
XXh
XXh
XXh
01000000b
XXh
XXXX0000b
00XX0000b
00XX0000b
00XX0000b
00h
00h
XXh
01000000b
XXh
XXh
01000000b
XXh
XXh
01000000b
XXh
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
000X0X0Xb
X0000000b
X0000000b
00h
XXh
XXh
XXh
00001000b
00000010b
XXh
XXh
Rev.2.00 Nov 28, 2005 page 26 of 378
REJ09B0124-0200