M16C6NK Datasheet, PDF (172/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
UARTi Transmit/Receive Mode Register (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0MR to U2MR
Address
03A0h, 03A8h, 01F8h
After Reset
00h
Bit
Symbol
SMD0
SMD1
SMD2
Bit Name
Function
RW
b2 b1 b0
0 0 0 : Serial interface disabled
RW
0 0 1 : Clock synchronous serial I/O mode
Serial Interface Mode _{0 1 0 : I}2_{C mode} (2)
Select Bit ⁽¹⁾
1 0 0 : UART mode transfer data 7-bit long ^RW
1 0 1 : UART mode transfer data 8-bit long
1 1 0 : UART mode transfer data 9-bit long _RW
Do not set a value except above
CKDIR
Internal/External Clock 0 : Internal clock
Select Bit
1 : External clock ⁽³⁾
RW
STPS
Stop Bit Length
Select Bit
0 : 1 stop bit
1 : 2 stop bits
RW
PRY
Odd/Even Parity
Select Bit
Effective when the PRYE bit = 1
0 : Odd parity
1 : Even parity
RW
PRYE Parity Enable Bit
0 : Parity disabled
1 : Parity enabled
RW
IOPOL
TXD, RXD I/O Polarity 0 : No reverse
Reverse Bit
1 : Reverse
RW
NOTES:
1. To receive data, set the corresponding port direction bit for each RXDi pin to "0" (input mode).
2. Set the corresponding port direction bit for SCL and SDA pins to "0" (input mode).
3. Set the corresponding port direction bit for each CLKi pin to "0" (input mode).
UARTi Transmit/Receive Control Register 0 (i = 0 to 2)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C0 to U2C0
Address
03A4h, 03ACh, 01FCh
After Reset
00001000b
Bit
Symbol
Bit Name
Function
RW
b1 b0
CLK0
0 0 : f1SIO or f2SIO is selected
RW
BRG Count Source _{0 1 : f8SIO is selected}
Select Bit ⁽⁵⁾
CLK1
1 0 : f32SIO is selected
1 1 : Do not set a value
RW
CTS/RTS Function
CRS _{Select Bit (1)}
Effective when CRD = 0
0 : CTS function is selected ⁽²⁾
1 : RTS function is selected
RW
Transmit Register
TXEPT _{Empty Flag}
0 : Data present in transmit register
(during transmission)
1 : No data present in transmit register ^RO
(transmission completed)
CRD
0 : CTS/RTS function enabled
CTS/RTS Disable Bit 1 : CTS/RTS function disabled
RW
(P6_0, P6_4, P7_3 can be used as I/O ports)
Data Output
NCH _{Select Bit (3)}
0 : TXDi/SDAi and SCLi pins are CMOS output
1 : TXDi/SDAi and SCLi pins are
RW
N channel open-drain output
CKPOL ^{CLK Polarity}
Select Bit
0 : Transmit data is output at falling edge
of transfer clock and receive data is
input at rising edge
1 : Transmit data is output at rising edge ^RW
of transfer clock and receive data is
input at falling edge
UFORM
Transfer Format
Select Bit ⁽⁴⁾
0 : LSB first
1 : MSB first
RW
NOTES:
1. CTS1/RTS1 can be used when the CLKMD1 bit in the UCON register = 0 (only CLK1 output) and the
RCSP bit in the UCON register = 0 (CTS0/RTS0 not separated).
2. Set the corresponding port direction bit for each CTSi pin to "0" (input mode)
3. SCL2(P7_1) is N channel open-drain output. The NCH bit in the U2C0 register is N channel open-drain
output regardless of the NCH bit.
4. The UFORM bit is enabled when the SMD2 to SMD0 bits in the UiMR register are set to "001b" (clock
synchronous serial I/O mode), or "101b" (UART mode, 8-bit transfer data).
Set this bit to "1" when the SMD2 to SMD0 bits are set to "010b" (I²C mode), and to "0" when the SMD2
to SMD0 bits are set to "100b" (UART mode, 7-bit transfer data) or "110b" (UART mode, 9-bit transfer data).
5. When changing the CLK1 to CLK0 bits, set the UiBRG register.
Figure 15.6 U0MR to U2MR Registers and U0C0 to U2C0 Registers
Rev.2.00 Nov 28, 2005 page 154 of 378
REJ09B0124-0200