M16C6NK Datasheet, PDF (173/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
UARTj Transmit/Receive Control Register 1 (j = 0, 1)
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U0C1, U1C1
Address
03A5h, 03ADh
After Reset
00XX0010b
Bit
Symbol
Bit Name
Function
RW
TE
Transmit Enable Bit
0 : Transmission disabled
1 : Transmission enabled
RW
Transmit Buffer
TI _{Empty Flag}
0 : Data present in the UjTB register
1 : No data present in the UjTB register ^RO
RE
Receive Enable Bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive Complete
Flag
0 : No data present in the UjRB register
1 : Data present in the UjRB register
RO
- ^{Nothing is assigned. When write, set to "0".}
(b5-b4) When read, their contents are indeterminate.
-
UjLCH
Data Logic
Select Bit ⁽¹⁾
0 : No reverse
1 : Reverse
RW
UjERE
Error Signal Output
Enable Bit
0 : Output disabled
1 : Output enabled
RW
NOTE:
1. The UjLCH bit is enabled when the SMD2 to SMD0 bits in the UjMR register are set to "001b" (clock
synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data) or "101b" (UART mode, 8-bit
transfer data).
Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I²C mode) or "110b" (UART mode, 9-bit
transfer data).
UART2 Transmit/Receive Control Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
U2C1
Address
01FDh
After Reset
00000010b
Bit
Symbol
Bit Name
Function
RW
TE
Transmit Enable Bit
0 : Transmission disabled
1 : Transmission enabled
RW
Transmit Buffer
TI _{Empty Flag}
0 : Data present in U2TB register
1 : No data present in U2TB register
RO
RE
Receive Enable Bit
0 : Reception disabled
1 : Reception enabled
RW
RI
Receive Complete
Flag
0 : No data present in U2RB register
1 : Data present in U2RB register
RO
U2IRS
UART2 Transmit Interrupt
Cause Select Bit
0 : Transmit buffer empty (TI bit = 1)
1 : Transmit is completed (TXEPT bit = 1)
RW
U2RRM
UART2 Continuous
Receive Mode Enable Bit
0 : Continuous receive mode disabled
1 : Continuous receive mode enabled
RW
U2LCH
Data Logic
Select Bit ⁽¹⁾
0 : No reverse
1 : Reverse
RW
U2ERE
Error Signal Output
Enable Bit
0 : Output disabled
1 : Output enabled
RW
NOTE:
1. The U2LCH bit is enabled when the SMD2 to SMD0 bits in the U2MR register are set to "001b" (clock
synchronous serial I/O mode), "100b" (UART mode, 7-bit transfer data) or "101b" (UART mode, 8-bit
transfer data).
Set this bit to "0" when the SMD2 to SMD0 bits are set to "010b" (I²C mode) or "110b" (UART mode, 9-bit
transfer data) .
Figure 15.7 U0C1, U1C1 Registers and U2C1 Register
Rev.2.00 Nov 28, 2005 page 155 of 378
REJ09B0124-0200