M16C6NK Datasheet, PDF (202/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
15.1.4 Special Mode 2
Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are
selectable. Table 15.14 lists the specifications of Special Mode 2. Figure 15.27 shows communication
control example for Special Mode 2. Table 15.15 lists the registers used in Special Mode 2 and the
register values set.
Table 15.14 Special Mode 2 Specifications
Item
Specification
Transfer data format
Transfer data length: 8 bits
Transfer clock
• Master mode
The CKDIR bit in the UiMR register = 0 (internal clock) : fj/ 2(n+1)
fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of the UiBRG register 00h to FFh
• Slave mode
The CKDIR bit = 1 (external clock selected) : Input from CLKi pin
Transmit/receive control
Controlled by input/output ports
Transmission start condition Before transmission can start, the following requirements must be met ⁽¹⁾
• The TE bit in the UiC1 register = 1 (transmission enabled)
Reception start condition
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Before reception can start, the following requirements must be met ⁽¹⁾
• The RE bit in the UiC1 register = 1 (reception enabled)
• The TE bit in the UiC1 register = 1 (transmission enabled)
• The TI bit in the UiC1 register = 0 (data present in the UiTB register)
Interrupt Request
For transmission, one of the following conditions can be selected
Generation Timing
• The UiIRS bit ⁽²⁾ = 0 (transmit buffer empty): when transferring data from the UiTB
register to the UARTi transmit register (at start of transmission)
• The UiIRS bit =1 (transfer completed): when the serial I/O finished sending data from
the UARTi transmit register
For reception
• When transferring data from the UARTi receive register to the UiRB register (at
Error detection
completion of reception)
Overrun error ⁽³⁾
This error occurs if the serial I/O started receiving the next data before reading the
UiRB register and received the 7th bit of the next data
Select function
Clock phase setting
Selectable from four combinations of transfer clock polarities and phases
i = 0 to 2
NOTES:
1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0
register = 0 (transmit data output at the falling edge and the receive data taken in at the rising edge of
the transfer clock), the external clock is in the high state; if the CKPOL bit = 1 (transmit data output at
the rising edge and the receive data taken in at the falling edge of the transfer clock), the external clock
is in the low state.
2. The U0IRS and U1IRS bits respectively are bits 0 and 1 in the UCON register ; the U2IRS bit is bit 4 in the
U2C1 register.
3. If an overrun error occurs, the value of UiRB register will be indeterminate. The IR bit in SiRIC register
does not change.
Rev.2.00 Nov 28, 2005 page 184 of 378
REJ09B0124-0200