M16C6NK Datasheet, PDF (212/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
15. Serial Interface
Figure 15.33 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply pull-up.
Microcomputer
TXD2
RXD2
SIM card
Figure 15.33 SIM Interface Connection
15.1.6.1 Parity Error Signal Output
The parity error signal is enabled by setting the U2ERE bit in the U2C1 register to “1”.
The parity error signal is output when a parity error is detected while receiving data. This is achieved by
pulling the TXD2 output low with the timing shown in Figure 15.32. If the R2RB register is read while
outputting a parity error signal, the PER bit is set to “0” and at the same time the TXD2 output is returned
high.
When transmitting, a transmission-finished interrupt request is generated at the falling edge of the transfer
clock pulse that immediately follows the stop bit. Therefore, whether a parity signal has been returned
can be determined by reading the port that shares the RXD2 pin in a transmission-finished interrupt
service routine.
Figure 15.34 shows the output timing of the parity error signal
Transfer "H"
clock "L"
RXD2 "H"
"L"
ST D0 D1 D2 D3 D4 D5 D6 D7 P SP
TXD2 "H"
"L"
RI bit in _"1"
U2C1 register "0"
(NOTE 1)
This timing diagram applies to the case where the direct format is
ST: Start bit
implemented.
P: Even Parity
NOTE:
SP: Stop bit
1: The output of microcomputer is in the high-impedance state (pulled up externally).
Figure 15.34 Parity Error Signal Output Timing
Rev.2.00 Nov 28, 2005 page 194 of 378
REJ09B0124-0200