M16C6NK Datasheet, PDF (94/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
8. Clock Generating Circuit
Main Clock Oscillation
PLL operation mode
CPU clock
: f(PLL)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
PLC07 = 1
CM11 = 1 ⁽⁶⁾
PLC07 = 0
CM11 = 0
High-Speed Mode
CPU clock
: f(XIN)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode
(divide by 2) (divide by 4) (divide by 8) (divide by 16)
CPU clock
: f(XIN)/2
CPU clock
: f(XIN)/4
CPU clock
: f(XIN)/8
CPU clock
: f(XIN)/16
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
CM07 = 0
CM06 = 1
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
On-chip Oscillator
Clock Oscillation
On-chip Oscillator
Mode
On-chip Oscillator
Low Power Dissipation Mode
CM21 = 0 (7)
CM21 = 1
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM05 = 0
CM05 = 1 ⁽¹⁾
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM04 = 1 CM04 = 0
CM04 = 1
CM04 = 0
High-Speed mode ^{Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode Medium-Speed Mode}
(divide by 2) (divide by 4) (divide by 8) (divide by 16)
CPU clock
: f(PLL)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
PLC07 = 1
CM11 = 1 ⁽⁶⁾
PLC07 = 0
CM11 = 0
CPU clock
: f(XIN)
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 0
CPU clock
: f(XIN)/2
CM07 = 0
CM06 = 0
CM17 = 0
CM16 = 1
CPU clock
: f(XIN)/4
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 0
CPU clock
: f(XIN)/8
CM07 = 0
CM06 = 1
CPU clock
: f(XIN)/16
CM07 = 0
CM06 = 0
CM17 = 1
CM16 = 1
PLL operation mode
CM07 =1 ⁽³⁾
CM07 = 0 ^{(2) (4)}
CM04 = 1
CM04 = 0
CM04 = 1
CM04 = 0
CM21 = 0 ⁽⁷⁾
CM21 = 1
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
CM05 = 0
CM05 = 1 ⁽¹⁾
CPU clock
f(Ring)
f(Ring)/2
f(Ring)/4
f(Ring)/8
f(Ring)/16
On-chip Oscillator
Mode
On-chip Oscillator
Low Power Dissipation Mode
Low-Speed Mode
CPU clock: f(XCIN)
CM07 = 0
CM21 = 0
CM21 = 1
Low-Speed Mode
CPU clock: f(XCIN)
CM07 = 0
CM05 = 1 ^{(1) (8)}
CM05 = 0
Low Power Dissipation Mode
CPU clock: f(XCIN)
CM07 = 0
CM06 = 1
CM15 = 1
Sub clock oscillation
CM04, CM05, CM06, CM07: Bits in CM0 register
CM11, CM15, CM16, CM17: Bits in CM1 register
CM20, CM21
: Bits in CM2 register
PLC07
: Bit in PLC0 register
NOTES:
1. Avoid making a transition when the CM20 bit is set to "1" (oscillation stop, re-oscillation detection function enabled).
Set the CM20 bit to "0" (oscillation stop, re-oscillation detection function disabled) before transiting.
2. Wait for the main clock oscillation stabilization time.
3. Switch clock after oscillation of sub clock is sufficiently stable.
4. Change the CM17 and CM16 bits before changing the CM06 bit.
5. Transit in accordance with arrow.
6. The PM20 bit in the PM2 register become effective when the PLC07 bit is set to "1" (PLL on). Change the PM20 bit when the PLC07 bit is
set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.
PM20 bit to "0" (SFR accessed with two wait states) before setting the PLC07 bit to "1" (PLL operation).
7. Set the CM06 bit to "1" (divide-by-8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.
8. When the CM21 bit = 0 (on-chip oscillator turned off) and the CM05 bit = 1 (main clock turned off), the CM06 bit is fixed to "1" (divide-by-8 mode)
and the CM15 bit is fixed to "1" (drive capability High).
Figure 8.13 State Transition in Normal Operation Mode
Rev.2.00 Nov 28, 2005 page 76 of 378
REJ09B0124-0200