M16C6NK Datasheet, PDF (80/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

Under development
This document is under development and its contents are subject to change.
M16C/6N Group (M16C/6NK, M16C/6NM)
8. Clock Generating Circuit
CAN0/1 Clock Select Register ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
Symbol
CCLKR
Address
025Fh
After Reset
00h
Bit Symbol
Bit Name
Function
RW
b2 b1 b0
CCLK0
0 0 0 No division
RW
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
CCLK1 CAN0 Clock Select Bits ^{(2) 0 1 1 : Divide-by-8}
RW
1 0 0: Divide-by-16
101:
CCLK2
1 1 0 : Do not set a value
RW
111:
CCLK3
CAN0 CPU Interface
Sleep Bit ⁽³⁾
0: CAN0 CPU interface operating
1: CAN0 CPU interface in sleep
RW
b6 b5 b4
CCLK4
0 0 0 No division
RW
0 0 1 : Divide-by-2
0 1 0 : Divide-by-4
CCLK5 CAN1 Clock Select Bits ^{(2) 0 1 1 : Divide-by-8}
RW
1 0 0: Divide-by-16
101:
CCLK6
1 1 0 : Do not set a value
RW
111:
CCLK7
CAN1 CPU Interface
Sleep Bit ⁽³⁾
0: CAN1 CPU interface operating
1: CAN1 CPU interface in sleep
RW
NOTES:
1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (Write enabled).
2. Set only when the Reset bit in the CiCTLR register (i = 0, 1) = 1 (Reset/Initialization mode).
3. Before setting this bit to "1", set the Sleep bit in the CiCTLR register to "1" (Sleep mode enabled).
Figure 8.6 CCLKR Register
Processor Mode Register 2 ⁽¹⁾
b7 b6 b5 b4 b3 b2 b1 b0
00
0
Symbol
PM2
Address
001Eh
After Reset
XXX00000b
Bit Symbol
Bit Name
Function
RW
Specifying Wait when
0 : 2 waits
PM20 ^{Accessing SFR at PLL}
1 : 1 wait
RW
Operation ⁽²⁾
-
(b1)
Reserved Bit
Set to "0"
RW
PM22
-
(b4-b3)
WDT Count Source
Protective Bit ^{(3) (4)}
Reserved Bit
0 : CPU clock is used for the
watchdog timer count source
1 : On-chip oscillator clock is used for ^RW
the watchdog timer count source
Set to "0"
RW
-
(b7-b5)
Nothing is assigned. When write, set to "0".
When read, their contents are indeterminate.
-
NOTES:
1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enable).
2. The PM20 bit become effective when the PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20
bit when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit t "0" (2 waits) when PLL clock > 16MHz.
3. Once this bit is set to "1", it cannot be set to "0" in a program.
4. Setting the PM22 bit to "1" results in the following conditions:
The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count source.
The CM10 bit in the CM1 register is disabled against write. (Writing a "1" has no effect, nor is stop mode entered.)
The watchdog timer does not stop when in wait mode or hold state.
Figure 8.7 PM2 Register
Rev.2.00 Nov 28, 2005 page 62 of 378
REJ09B0124-0200