M16C6NK Datasheet, PDF (336/404 Pages) Renesas Technology Corp – 16-BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY / M16C/60 SERIES

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M16C/6N Group (M16C/6NK, M16C/6NM)
22. Electric Characteristics (Normal-ver.)
Switching Characteristics
VCC = 3.3V
(Referenced to VCC = 3.3V, VSS = 0 V, at Topr = –40 to 85 °C unless otherwise specified)
Table 22.44 Memory Expansion Mode and Microprocessor Mode (for 1- to 3-wait setting and external area access)
Symbol
Parameter
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
td(BCLK-ALE)
th(BCLK-ALE)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(BCLK-DB)
th(BCLK-DB)
td(DB-WR)
th(WR-DB)
td(BCLK-HLDA)
Address output delay time
Address output hold time (refers to BCLK)
Address output hold time (refers to RD)
Address output hold time (refers to WR)
Chip select output delay time
Chip select output hold time (refers to BCLK)
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (refers to BCLK)
Data output hold time (refers to BCLK) ⁽³⁾
Data output delay time (refers to WR)
Data output hold time (refers to WR) ⁽³⁾
__________
HLDA output delay time
Measuring
condition
Figure 22.12
Standard
Unit
Min.
Max.
30
ns
4
ns
0
ns
(NOTE 1)
ns
30
ns
4
ns
25
ns
–4
ns
30
ns
0
ns
30
ns
0
ns
40
ns
4
ns
(NOTE 2)
ns
(NOTE 1)
ns
40
ns
NOTES:
1. Calculated according to the BCLK frequency as follows:
0.5 ✕ 10⁹ _{– 10 [ns]}
f(BCLK)
2. Calculated according to the BCLK frequency as follows:
(n – 0.5) ✕ 10⁹
– 40 [ns]
f(BCLK)
n is “1” for 1-wait setting, “2” for 2-wait setting and “3” for 3-wait setting.
When n = 1, f(BCLK) is 12.5 MHz or less.
3. This standard value shows the timing when the
output is off, and does not show hold time of
data bus.
Hold time of data bus varies with capacitor volume
and pull-up (pull-down) resistance value.
Hold time of data bus is expressed in
t = – CR ✕ ln (1 – VOL / VCC)
by a circuit of the right figure.
For example, when VOL = 0.2 VCC, C = 30 pF,
R =1 kΩ, hold time of output “L” level is
t = – 30 pF ✕ 1 kΩ ✕ ln (1 – 0.2 VCC / VCC) = 6.7 ns..
R
DBi
C
Rev.2.00 Nov 28, 2005 page 318 of 378
REJ09B0124-0200