450NX Datasheet, PDF (99/248 Pages) Intel Corporation – Intel 450NX PCIset

Transaction Summary ₇
This chapter describes the transactions supported by the Intel^® 450NX PCIset.
7.1 Host To/From Memory Transactions
7.1.1
Reads and Writes
The Read transactions supported by the Intel 450NX PCIset are: Partial Reads, Part-line Reads,
Cache Line Reads, Memory Read and Invalidate (length > 0), Memory Read and Invalidate (length =
0), Memory Read (length = 0).
The Write transactions supported by the Intel 450NX PCIset are: Partial Writes, Part-line Writes,
Cache Line Writes.
7.1.2
Cache Coherency Cycles
The MIOC implements an implicit writeback response during system bus read and write
transactions when a system bus agent asserts HITM# during the snoop phase. In the read case
the MIOC snarfs the writeback data and updates the DRAM. The write case has two data
transfers: the requesting agent’s data followed by the snooping agent’s writeback data.
7.1.3
Interrupt Acknowledge Cycles
A processor agent issues an Interrupt Acknowledge cycle in response to an interrupt from an
8259-compatible interrupt controller. The Interrupt Acknowledge cycle is similar to a partial
read transaction, except that the address bus does not contain a valid address. The interrupt
acknowledge request issued by the processor is deferred by the MIOC and forwarded to PXB
#0, which performs a PCI Interrupt Acknowledge cycle on PCI bus #0A (the compatibility PCI
bus).
7.1.4
Locked Cycles
The system bus specification provides a means of performing a bus lock. Any Host-PCI locked
transaction will initiate a PCI locked sequence. The processor implements the bus lock
Intel® 450NX PCIset
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