450NX Datasheet, PDF (36/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
Table 3-1 illustrates the MIOC’s Configuration Space Map. Many of these registers affect both
host-initiated transactions and PCI-initiated transactions, and are therefore duplicated in both
the MIOC and PXB Configuration Spaces. It is software’s responsibility to ensure that both
sets of registers are programmed consistently to achieve correct operation.
3.3.1
BUFSIZ: Buffer Sizes
Address Offset: 48-4Ah
Default Value: 304310h
Bits Description
Size:
24 bits
Attribute: Read Only
23:18
Inbound Write Transaction Capacity.
Total number of inbound write transactions, per Expander Port, that can be accepted
by the MIOC.
Value=12.
17:12
Inbound Read Transaction Capacity.
Total number of inbound read transactions, per Expander Port, that can be accepted
by the MIOC.
Value=4.
11:6 Inbound Write Data Buffer Capacity.
Total number of data buffers, per Expander Port, available in the MIOC for use by
inbound write transactions, in increments of 32 bytes.
Value=12.
5:0 Inbound Read Data Buffer Capacity.
Total number of data buffers, per Expander Port, available in the MIOC for use by
inbound read transactions, in increments of 32 bytes.
Value=16.
3-4
Intel® 450NX PCIset