450NX Datasheet, PDF (89/248 Pages) Intel Corporation – Intel 450NX PCIset

Interfaces ₅
5.1
System Bus
The host interface of the Intel^® 450NX PCIset is targeted toward Pentium^® II Xeon™
processor-based multiprocessor systems, and is specifically optimized for four processors
sharing a common bus with bus clock frequencies of 100 MHz. The MIOC provides the
system bus address, control and data interfaces for the Intel 450NX PCIset, and represents a
single electrical load on the system bus.
The Intel 450NX PCIset recognizes and supports a large subset of the transaction types that
are defined for the P6 family processor’s bus interface. However, each of these transaction
types have a multitude of response types, some of which are not supported by this controller.
The responses that are supported by the MIOC are: Normal without Data, Normal with Data,
Retry, Implicit Write Back, Deferred Response. Refer to the chapter on Transactions for more
details on the transaction types supported by the Intel 450NX PCIset.
5.2
PCI Bus
Each PXB provides two independent 32-bit, 33 MHz Rev. 2.1-compliant PCI interfaces which
support 5 volt or 3 volt PCI devices. Each bus will support up to 10 electrical loads, where the
PXB and the PIIX4E south bridge each represent one load, and each connector/device pair
represents two loads. The internal bus arbiter supports six PCI bus masters in addition to the
PXB itself and the south bridge on the compatibility bus. The compatibility bus is always bus
#0A (PXB #0, Bus A).
The PCI buses are operated synchronously with the system bus, using the system bus clock as
the master clock. A system bus/PCI bus clock ratio of 3:1 supports the Intel Pentium^® II
Xeon™ processor at 100 MHz with 33.3 MHz PCI bus, or a degraded 90 MHz system bus with
a 30 MHz PCI bus (or lower, depending on the effect of the 6th load on the system bus).
A configuration option allows the two 32-bit PCI buses (A and B) on a single PXB to be
operated in combination as a single 64-bit PCI bus. Bus A data represents the low Dword,
while bus B data represents the high Dword.
5.3
Expander Bus
The Expander Interface provides a bidirectional path for data and control between the PXB
and MIOC components. The Expander bus consists of a 16 bit wide data bus which carries
command, address, data, and transaction information. There are two additional bits that carry
Intel® 450NX PCIset
5-1