450NX Datasheet, PDF (116/248 Pages) Intel Corporation – Intel 450NX PCIset

11. Clocking and Reset
Pull-up/Pull-down
Detect
Host CLK/ 3
VCC
PCLK
PCLKFB
PXB
External Low Skew
Clock Driver
A _Y1
Y2
Y3
Yn
Figure 11-2: PCI Clock Generation and Distribution
11.2 System Reset
Five varieties of reset functions are supported by the Intel^® 450NX PCIset.
– A Power-Good Reset is triggered by an externally generated signal which indicates that
the power supplies and clocks are stable. This reset clears all configuration and
transaction state in the Intel 450NX PCIset, as well as asserting resets to the
processors, PCI buses, and PIIX, if present.
– A System Hard Reset is a software-initiated reset that performs nearly the same
functions as the power-good reset. The key difference is that the system hard reset
does not clear "sticky" error flags in the Intel 450NX PCIset, thus allowing an error
handler to determine the cause of a failure that resulted in reset. Also, hard reset may
optionally trigger the processor’s Built-In Self-Test (BIST).
– A Soft Reset is another software-initiated reset which affects only the processors. This
reset may also be generated by certain I/O activities.
– A BINIT Reset results from a catastrophic transaction error on the system bus. The
memory and the MIOC’s configuration space are untouched.
– A PXB Reset is a software-initiated reset that affects only a single PXB and its
dependent PCI buses. This reset may be used in high-availability systems, where it is
desirable to allow the processors and one PXB to continue operation in the event of
failure of a single PXB.
11.2.1 Intel^® 450NX PCIset Reset Structure
Figure 11-3 shows the recommended reset structure for an Intel 450NX PCIset-based system
including the PIIX4E south bridge. Note that the primary system power-good signal is
provided to the MIOC, which then distributes a variety of reset signals to the rest of the
system.
11-2
Intel® 450NX PCIset