450NX Datasheet, PDF (84/248 Pages) Intel Corporation – Intel 450NX PCIset

4. System Address Maps
Top of Memory and Expansion Gaps
A “Top of Memory” pointer identifies the highest memory-mapped address that can be
serviced by this node. Accesses to addresses above this pointer will not be directed to local
memory or the PCI buses, but will be allowed to sit unclaimed on the system bus. A third-
party agent on the system bus may claim such accesses, either servicing them with its own
local resources or forwarding them to other nodes for service (i.e., a cluster bridge). Any
access that remains unclaimed will eventually timeout in the Intel 450NX PCIset; on timeout
the access is claimed by the Intel 450NX PCIset and terminated.
Below the Top of Memory, there are two programmable expansion gaps: the Low Expansion
Gap and the High Expansion Gap. Each gap, if enabled, opens a “hole” in the physical address
space, where accesses will not be directed to memory. Instead, these accesses may be directed
to one of the PCI buses, or will be allowed to sit unclaimed on the system bus where they may
be claimed by a third-party agent, as above.
Both expansion gaps are defined using base and top addresses, on 1MB boundaries. The Low
Expansion Gap must be located above the Low Compatibility Region, and below the High
Expansion Gap, the 4 GB boundary, and the Top of Memory. The High Expansion Gap must
be located above the enabled Low Expansion Gap, above 1MB, and below the Top of Memory.
At power-on, both gaps are disabled.
4.1.1
Memory-Mapped I/O Spaces
The Intel^® 450NX PCIset provides two programmable I/O spaces: the Low ISA Space and the
PCI Space. Both spaces allow accesses to be directed to a PCI bus. Any region defined as
memory-mapped I/O must have a UC (UnCacheable) memory type, set in the Pentium II
Xeon processor’s MTTR registers.
Low ISA Space
The Low ISA Space is provided to support older ISA devices which cannot be relocated above
the 16 MB address limit of older systems. Accesses to this space will be directed down to the
compatibility PCI bus (0A). The Low ISA Space can start on any 1 MB boundary below 16 MB,
and can be of size 1, 2, 4 or 8 MB.
PCI Space
The PCI Space consists of four contiguous address ranges, allowing accesses to be directed to
each of the four PCI buses supported by the Intel 450NX PCIset. Each address range
corresponds to a PCI bus, and is configurable on 1 MB boundaries.
4.1.2
SMM RAM Support
Intel Architecture processors include a System Management Mode (SMM) that defines a
protected region of memory called SM RAM. The Intel 450NX PCIset allows an SM RAM
region to be defined and enabled. When enabled, memory reads and writes to addresses that
fall within the SM RAM address range are protected accesses. If the configuration enables
permit access, and the requesting agent asserts SMMEM# (priveleged access), the MIOC will
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Intel® 450NX PCIset