450NX Datasheet, PDF (103/248 Pages) Intel Corporation – Intel 450NX PCIset

7.3 Inbound Transactions
indeterminate results. Assertion of DEFER# during an outbound transaction will also have
indeterminate results.
7.3
Inbound Transactions
For all inbound transactions, the Intel^® 450NX MIOC will use an Agent ID of ‘1001b (9). This
is the same agent ID used by the Intel 450GX PCIset, which the Intel 450NX PCIset replaces.
Note that memory-mapped accesses across PCI buses (i.e., peer-to-peer transfers) are not
supported. Also, inbound I/O transactions are not supported, either to other PCI buses or to
the system bus.
7.3.1
Inbound LOCKs
Inbound (PCI-to-system bus) LOCKs are not supported in the Intel 450NX PCIset. Use of
inbound locks on the Intel 450NX PCIset may result in unanticipated behavior. The Intel
450NX PCISet is NOT compatible with devices on the compatibility PCI bus which are
capable of initiating inbound bus- or resource-locks. Deadlock may occur between outbound
locked transactions, south bridge-initiated Secure Sideband Requests (PHOLD#), and LOCK#
assertion by the offending device. Devices capable of asserting LOCK# to access memory
should not be used on the compatibility PCI bus.
7.3.2
South Bridge Accesses
The PXB’s Bus ‘a’ has sideband signals to support the PIIX4E south bridge for ISA expansion.
The PXB does not support an EISA bridge.
WSC# Handshake
When the PIIX4E south bridge issues an interrupt for an ISA master, it must first check that
any writes posted from ISA to memory have been observed before the interrupt is issued.
This action is necessary to guarantee that an ISA write followed by an ISA interrupt is
observed in that same order by a processor on the system bus.
Whenever the compatibility bus PXB receives a write from the south bridge, it will deassert
the WSC# (Write Snoop complete) signal. WSC# will remain de-asserted until the write
Completion for that write has returned. When the Completion returns, WSC# is again
asserted. While WSC# is de-asserted the PXB must retry any additional writes from the south
bridge.
The PXB will only support the WSC# Handshake when the internal arbiter is used. When
operating in external arbiter mode, the PXB will always hold WSC# asserted. The WSC#
mode may be disabled by a bit in the PXB’s CONFIG register. If disabled, WSC# stays
asserted and inbound writes from the south bridge are accepted.
Intel® 450NX PCIset
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