450NX Datasheet, PDF (57/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
1
System Hard Reset Enable (SHRE).
This bit modifies the action of the RCPU bit, above. If set, the Intel^® 450NX PCIset
will initiate a system hard reset upon a subsequent 0-to-1 transition of the RCPU bit. If
this bit is cleared, the Intel 450NX PCIset will initiate a soft reset upon a subsequent 0-
to-1 transition of the RCPU bit. Default=0.
0
reserved (0)
3.3.35 RCGP: RCGs Present
Address Offset: A3h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
The Intel 450NX PCIset memory subsystem supports at most two RCGs (one per card). This
corresponds to RCG #0 and RCG #2, bits 0 and 2 in the RCGP register.
Bits Description
7:4 reserved (0)
3:0 RCGs Present [3:0].
If bit i is set, then RCG[i] was detected as present in the system following power-on
reset. If cleared, then RCG[i] is not present. Default= <hardware generated>.
3.3.36 REFRESH: DRAM Refresh Control Register
Address Offset: A4-A5h
Default Value: 0411h
Size:
16 bits
Attribute: Read/Write
Bits Description
15:11 reserved (0)
10:0 Refresh Count.
Specifies the number of system bus cycles between refresh cycles. Typically, the value
is chosen to provide a refresh at least every 15.625 usec.
@ 100.0 MHz: 61Ah = 15.620 usec
@ 90.0 MHz: 57Eh = 15.622 usec
Maximum value is 20.48 usec at 100 MHz.
Default=411h
3.3.37 RID: Revision Identification Register
Address Offset: 08h
Default Value: 00h
Size:
8 bits
Attribute: Read Only
Intel® 450NX PCIset
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