450NX Datasheet, PDF (25/248 Pages) Intel Corporation – Intel 450NX PCIset

2.5 Memory Subsystem Interface
RCGs across both cards while excluding the MIOC. This allows all RCGs to
monitor each request completion without placing undue loading on the
RCMPLT# signals.
MRESET#
Memory Subsystem Reset
AGTL+ MIOC→ RCG/MUX
This signal represents a hard reset of the memory subsystem. It is asserted
following PWRGD or upon the MIOC issuing a processor RESET due to
software invocation.
RCMPLTa#
RCMPLTb#
Request Complete
AGTL+ RCG→ MIOC
This signal, which is driven by the currently active RCG, indicates the
completion of a request into the memory array. Typically the “a” signal
connects the MIOC and all RCGs on Card #0, while the “b” signal connects
the MIOC and all RCGs on Card #1.
PHIT(a,b)#
RHIT(a,b)#
Page and Row Hit Status
AGTL+ RCG→ MIOC
These signals indicate what resource, if any, delayed the initiation of a read.
Typically the “a” signal connects the MIOC and all RCGs on Card #0, while
the “b” signal connects the MIOC and all RCGs on Card #1.
DSTBP[3:0]#
DSTBN[3:0]#
Data Strobes
AGTL+ MUX↔ MIOC
This set of four signal-pairs are strobes which qualify the data transferred
between the MUX and MIOC. Each strobe pair qualifies 18 bits (two bytes
and two check bits), as follows:
DSTB[0]# qualifies MD[17:00]#.
DSTB[1]# qualifies MD[35:18]#.
DSTB[2]# qualifies MD[53:36]#.
DSTB[3]# qualifies MD[71:54]#.
In a 4:1 interleaved system, with 2 MUXs per card, DSTB[1:0]# strobes the
low MUX and DSTB[3:2]# strobes the high MUX. In a 2:1 interleaved system,
with only a single MUX per card, DSTB[1:0]# strobes the MUX, and
DSTB[3:2]# is not used.
MD[71:36]#
MD[35:00]#
Memory Data
AGTL+ MUX↔ MIOC
These signals are connected to the external datapath of the MUXs. Each MUX
provides 36 bits of the 72-bit datapath to the MIOC.
DCMPLTa#
DCMPLTb#
AGTL+ MUX→ MIOC/MUX
Data Transfer Complete
MIOC→ MUXs
This signal is driven by the source of the data transfer: the MIOC for writes,
and the MUX for reads. DCMPLT# active indicates that the data transfer is
complete. Typically the “a” signal connects the MIOC and all MUXs on Card
#0, while the “b” signal connects the MIOC and all MUXs on Card #1.
DOFF[1:0]#
Data Offset
AGTL+ MIOC→ MUX
These two bits, when qualified by the DVALID# signal, define the initial
Qword access order for the data transfer. The result is that the critical chunk
is accessed first and the remaining chunks are accessed in Intel “Toggle”
order.
Intel® 450NX PCIset
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