450NX Datasheet, PDF (97/248 Pages) Intel Corporation – Intel 450NX PCIset

6.1 Overview
6.1.3
Address Bit Permuting
Address Bit Permuting works by increasing the likelihood that requests spaced closely
together in time access different banks of memory which will already be closed and
precharged.
This is achieved by distributing the addresses, on a cache line size granularity, across either
two or four banks of memory. The lowest order address bits which define a cache line are
used as the bank selects into the memory array so that all requests to a zero based cache line
are directed at bank 0. This is illustrated in Figure 6-4.
4 Bank Permuting
Bank 0
Bank 1
Bank 2
Bank 3
Request address accesses bank:
0h, 80h, 100h, ....
20h, A0h, 120h, ...
40h, C0h, 140h, ...
60h, E0h, 160h, ...
2 Bank Permuting
Bank 0
Bank 1
Request address accesses bank:
0h, 40h, 80h, ....
20h, 60h, A0h, ...
Figure 6-4: Effect of Address Bit Permuting on Bank Access Order
6.1.4
Card to Card (C2C) Interleaving
The purpose of the C2C feature is to further distribute memory accesses across multiple banks
of memory as done with the ABP modes. This mode is supported in addition to the standard
ABP modes so that maximum distribution of memory accesses and hence, maximum
sustained bandwidth can be acheived.
The distribution of accesses to each memory card with C2C enabled is by cache line with all
even cache lines sent to Card 0 and all odd cache lines sent to Card 1. The feature can be
enabled, if all of the restricions are met, by setting bit 2 of the MIOC CONFIG register.
With C2C enabled the DRAM Bank Configuration Registers become mapped to the physical
memory differently than with C2C disabled (default mode). Figure 6-5 shows both the C2C
disabled and enabled modes mapping of DRAM Bank Configuration Registers to physical
bank location.
With C2C enabled and 2 bank ABP enabled Banks 0, 1, 2 and 3 must all be the same size and
type and Banks 4, 5, 6 and 7 (if present) must be the same size and type.
With C2C enabled and 4 bank ABP enabled Banks 0 through 7 must all be the same size and
type.
Intel® 450NX PCIset
6-5