450NX Datasheet, PDF (98/248 Pages) Intel Corporation – Intel 450NX PCIset

6. Memory Subsystem
With C2C enabled and no ABP enabled each pair of consecutive banks must be of the same
size and type. For example Banks 0 and 1 must be the same size and type and Banks 2 and 3
must be the same size and type but need not match Banks 0 and 1.
C2C Disabled Bank Register Ordering
Bank 0
Bank 1
Bank 2
Bank 3
Memory Card 0
Bank 8
Bank 9
Bank 10
Bank 11
Memory Card 1
C2C Enabled Bank Register Ordering
Bank 0
Bank 2
Bank 4
Bank 6
Bank 1
Bank 3
Bank 5
Bank 7
Memory Card 0
Memory Card 1
Figure 6-5: DRAM Bank Configuration Register Programming with C2C
Disabled and Enabled
6.1.5
Memory Initialization
The MIOC provides an MRESET# output, which is asserted on power-good reset, system
hard reset, and a BINIT reset. The MRESET# signal is sent to all RCGs and MUXs in the
memory subsystem. When asserted, each RCG and MUX clears their transaction queues, data
buffers and transaction state. Any transactions that may have been in-progress or pending in
the memory subsystem are lost. Note that this may corrupt the contents of the DRAMs, and
could leave the DRAMs themselves in an intermediate state, unable to accept a new
transaction. Following MRESET# deassertion, the MIOC will re-initialize the memory
subsystem by issuing eight CAS#-before-RAS# refreshes per bank (this does not affect the
data held in the memory).
6-6
Intel® 450NX PCIset