450NX Datasheet, PDF (100/248 Pages) Intel Corporation – Intel 450NX PCIset

7. Transaction Summary
mechanism which means that no change of bus ownership can occur from the time the agent
has established the locked sequence (i.e., asserts LOCK# signal on the first transaction and
data is returned) until it is completed. The DRAM is locked from the PCI perspective until the
host locked transaction is completed.
7.1.5
Branch Trace Cycles
An agent issues a Branch Trace Cycle for taken branches if execution tracing is enabled. The
address Aa[35:3]# is reserved and can be driven to any value. D[63:32]# carries the linear
address of the instruction causing the branch and D[31:0]# carries the target linear address.
The MIOC will respond and retire this transaction but will not latch the value on the data lines
or provide any additional support for this type of cycle.
7.1.6
Special Cycles
Special cycles are used to indicate to the system some internal processor conditions. The first
address phase Aa[35:3]# is undefined and can be driven to any value. The second address
phase, Ab[15:8]# defines the type of Special Cycle issued by the processor. Table 7-1 below
specifies the cycle type and definition as well as the action taken by the MIOC when the
corresponding cycles are identified.
Table 7-1: MIOC Actions on Special Cycles
Ab[15:8] Cycle Type
Action Taken
0000 0000
0000 0001
0000 0010
0000 0011
0000 0100
0000 0101
0000 0110
0000 0111
all others
NOP
Shutdown
Flush
Halt
Sync
Flush
Acknowledge
Stop Clock
Acknowledge
SMI
Acknowledge
Reserved
This transaction has no side-effects.
This cycle is claimed by the MIOC. No corresponding cycle
is delivered to the PCI bus. The MIOC asserts INIT# back to
the agent for a minimum of 4 clocks.
The MIOC claims this cycle and retires it.
This cycle is claimed by the MIOC, forwarded to the
compatability PCI bus as a Special Halt Cycle, and retired
on the system bus after it is terminated on the PCI bus via a
master abort mechanism.
The MIOC claims this cycle and retires it.
The MIOC claims this cycle and retires it.
This cycle is claimed by the MIOC and propagated to the
PCI bus as a Special Stop Grant Cycle. It is completed on the
system bus after it is terminated on the PCI bus via a master
abort mechanism.
The MIOC’s SMIACT# signal will be asserted upon
detecting an SMI Acknowledge cycle with SMMEM#
asserted, and will remain asserted until detecting a
subsequent SMI Acknowledge cycle with SMMEM#
deasserted.
7-2
Intel® 450NX PCIset