450NX Datasheet, PDF (118/248 Pages) Intel Corporation – Intel 450NX PCIset

11. Clocking and Reset
MRESET#
The MRESET# signal is sent to all RCGs and MUXs in the memory subsystem. When
asserted, each RCG and MUX clears their transaction state and data buffers. Any transactions
that may have been in-progress or pending in the memory subsystem are lost. Upon
MRESET# deassertion, the MIOC will re-initialize the memory subsystem by issuing 8 CAS-
before-RAS refreshes per bank (this does not affect the data held in the memory).
Bus CLK
PWRGD
2ms req’d
1ms
Core & Exp.
Clocks
Internal
Reset#
MRESET#
RESET#
CRESET#
BNR#
X(0,1)RST#
2ms
tristate
2 Hclk
2ms
Expander Buses
Core Clock
PCI CLK
PWRGDB
Internal
Reset#
P(A,B)RST#
= PIIX4E PWROK
RSTDRV
CPURST
= PXB PIIXOK#
held in reset
resynch
ready
1ms
relock (1ms)
1ms
1ms req’d
Figure 11-4: Power-Good Reset
1ms
2ms
11-4
Intel® 450NX PCIset