450NX Datasheet, PDF (30/248 Pages) Intel Corporation – Intel 450NX PCIset

2. Signal Descriptions
VREF (n)
AGTL+ Reference Voltage
Analog I
This is the reference voltage derived from the termination voltage to the pull-
up resistors. The MIOC has 6 VREF pins, while the PXB, RCG and MUX each
have 2 VREF pins.
2.8 Component-Specific Support Signals
2.8.1
MIOC
CRESET#
ERR[1:0]#
HCLKIN
INTREQ#
PWRGD
PWRGDB
RESET#
Clock Selection Reset.
LVTTL O
This is a delayed version of the RESET# signal provided to the processors.
This signal is asserted asynchronously along with RESET#, but is deasserted
two system bus clocks following the deassertion of RESET#.
Error Code
LVTTL I/OD
These pins reflect irrecoverable errors detectable by the Intel 450NX PCIset.
ERR
Error Type
Associated Error s Flags
00 No error
01 PCIset Internal Error Expander Bus Parity
10 Multi-Bit Memory Error Multi-Bit Memory ECC error
11 System Bus Error
Address Parity, Request Parity, Protocol
Violation, BERR, Multi-Bit Host ECC error
Host Clock In
2.5V I
This pin receives a buffered system clock. This is a single trace from the clock
synthesizer to minimize clock skew.
Interrupt Request
LVTTL O
This pin is asserted by the MIOC when an internal event occurs and sets a
status flag, and that flag has been configured to request an interrupt.
Power Good
LVTTL I
This pin should be connected to a 3.3 V version of the system’s power good
indicator, and should be asserted only after all power supplies and clocks
have reached their stable references and been stable for at least 1 msec.
Buffered Power Good
LVTTL O
A buffered (but not synchronized) version of the PWRGD input, which is
used to drive the PWRGD input on each PXB in the system.
Reset
AGTL+ I/O
In normal operation, this signal is an output. The MIOC will reset the system
bus either on power-up or when programmed through the Reset Control
register.
2-18
Intel® 450NX PCIset