450NX Datasheet, PDF (21/248 Pages) Intel Corporation – Intel 450NX PCIset

2.4 PCI Interface
PpAD[31:0]
PCI Address/Data
PCI I/O
PCI Address and Data signals are multiplexed on this bus. The physical byte
address is output during the address phase and the data follows in the
subsequent data phase(s).
PpC/BE[3:0]#
Command/Byte Enable
PCI I/O
PCI Bus Command and Byte Enable signals are multiplexed on the same pins.
During the address phase of a transaction, C/BE[3:0]# define the bus
command. During the data phase C/BE[3:0]# are used as byte enables.
PpCLK
PCI Clock
LVTTL O
This signal is an output with a derived frequency equal to 1/3 of the system
bus frequency.
PpCLKFB
PCI Clock Feedback
LVTTL I
This signal is connected to the output of a low skew PCI clock buffer tree. It is
used to synchronize the PCI clock driven from PpCLK to the clock used for
the internal PCI logic.
PpDEVSEL#
Device Select
PCI I/ O
DEVSEL# is driven by the device that has decoded its address as the target of
the current access.
PpFRAME#
Frame
PCI I/O
The PXB asserts FRAME# to indicate the start of a bus transaction. While
FRAME# is asserted, data transfers continue. When FRAME# is negated, the
transaction is in the final data phase. FRAME# is an input when the PXB acts
as a PCI target.
PpIRDY#
Initiator Ready
PCI I/O
This signal is asserted by a master to indicate its ability to complete the
current data transfer. IRDY# is an output when the PXB acts as a PCI initiator
and an input when the PXB acts as a PCI target.
PpPAR
Parity
PCI I/O
PAR is driven by the PXB when it acts as a PCI initiator during address and
data phases for a write cycle, and during the address phase for a read cycle.
PAR is driven by the PXB when it acts as a PCI target during each data phase
of a PCI memory read cycle. Even parity is generated across AD[31:0] and
C/BE[3:0]#.
PpRST#
PCI Reset
PCI O
PCI Bus Reset forces the PCI interfaces of each device to a known state. The
PXB generates a minimum 1 ms pulse on RST#.
PpPERR#
PCI Parity Error
PCI I/O
Pulsed by an agent receiving data with bad parity one clock after PAR is
asserted. The PXB will generate PERR# active if it detects a parity error on
the PCI bus and the PERR# Enable bit in the PCICMD register is set.
PpLOCK#
Lock
PCI I/O
LOCK# indicates an exclusive bus operation and may require multiple
transactions to complete. It is possible for different agents to use the PCI Bus
while a single initiator retains ownership of the LOCK# signal.
Intel® 450NX PCIset
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