450NX Datasheet, PDF (63/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
3.4.1
BUFSIZ: Buffer Sizes
Address Offset: 48-4Ah
Size:
24 bits
Default Value: 302308h (64-bit bus mode)Attribute: Read Only
182184h (32-bit bus mode)
This register contains the hardwired information defining the maximum number of outbound
transactions and data bytes that this PXB/PCI port can accept.
Bits Description
23:18
Outbound Write Transaction Capacity.
This field specifies the total number of outbound write transactions that can be
accepted and queued in this PXB/PCI port.
Value= 6 (32-bit bus mode)
12 (64-bit bus mode)
17:12
Outbound Read Transaction Capacity.
This field specifies the total number of outbound read transactions that can be
accepted and queued in this PXB/PCI port.
Value= 2 (32-bit bus mode)
2 (64-bit bus mode)
11:6 Outbound Write Data Buffer Capacity.
This field specifies the total number of data buffers available in this PXB/PCI port for
use by outbound write transactions, in increments of 32 bytes.
Value= 6 (x 32 bytes) (32-bit bus mode)
12 (x 32 bytes) (64-bit bus mode)
5:0 Outbound Read Data Buffer Capacity.
This field specifies the total number of data buffers available in this PXB/PCI port for
use by outbound read transactions, in increments of 32 bytes.
Value= 4 (x 32 bytes) (32-bit bus mode)
8 (x 32 bytes) (64-bit bus mode)
3.4.2
CLASS: Class Code Register
Address Offset: 09 - 0Bh
Default Value: 060000h
Size:
24 bits
Attribute: Read Only
Bits Description
23:16 Base Class
For the PXB, this field is hardwired to 06h.
15:8 Sub-Class
For the PXB, this field is hardwired to 00h.
7:0 Register-Level Programming Interface
For the PXB, this field is hardwired to 00h.
Intel® 450NX PCIset
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