450NX Datasheet, PDF (107/248 Pages) Intel Corporation – Intel 450NX PCIset

8.3 South Bridge Support
8.3.2
PHOLD#/PHLDA# Protocol
The PIIX4E uses only two signals to obtain the ownership of the PCI bus. The PIIX4E will
assert PHOLD# to indicate that an ISA master is requesting to run a cycle (DREQ active) or an
integrated PCI-IDE bus-mastering device is requesting the PCI bus.
DREQ#
DGNT#
<PCI req
from PIIX>
PHOLD#
passive
bus
release
passive
bus
release
PHLDA#
<Host-PCI
writes
disabled>
<other
PCI
trans>
Figure 8-2: PHOLD#/PHLDA# Protocol Showing Active
and Passive Bus Release
active
bus
release
8.3.3
WSC# Protocol
The WSC# (Write Snoop Complete) is a status signal output from the Intel 450NX PCIset PXB.
The WSC# assertion indicates that all necessary snoops for a previously posted PCI-DRAM
write have been completed on the system bus.
The WSC# signal is primarily used by the I/O APIC device connected to the ISA bridge. The
I/O APIC uses this signal to maintain data coherency and ordering of transactions in the
system.
NOTE
The WSC# Handshake only applies if the PXB is in internal arbiter mode.
Intel® 450NX PCIset
8-3