450NX Datasheet, PDF (115/248 Pages) Intel Corporation – Intel 450NX PCIset

Clocking and Reset ₁₁
This chapter describes the generation, distribution and interaction between the various clocks
in an Intel^® 450NX PCIset-based system, as well as the various reset functionality supported
by the Intel 450NX PCIset.
11.1 Clocking
The Pentium^® II Xeon™ processor uses a clock ratio scheme where the system bus clock
frequency is multiplied to produce the processor’s core frequency. The MIOC supports a
system bus frequency optimized for 100 MHz. The Intel^® 450NX PCIset should be used at a
bus frequency which provides the required clock frequency for the PCI interfaces. The
external clock generator is responsible for generating the system clock. The Intel 450NX
PCIset’s core clock is equal to the system bus clock rate. The Intel 450NX PCIset is responsible
for driving the signals which the processor uses to determine the core to bus clock ratio.
The MIOC receives an output of a clock generator on the HCLKIN pin, as illustrated in Figure
11-1. The MIOC uses the HCLKIN signal to drive the host and memory interfaces and the core.
This clock is doubled for the MD bus and the Expander buses.
External Low Skew
Clock Driver
System Bus CLK
Y1
Y2
Y3
Yn
MIOC
HCLKIN
Figure 11-1: Host Clock Generation and Distribution
PCI clock distribution is illustrated in Figure 11-2. The PXB provides a PCI bus clock that is
generated by dividing the internal host clock frequency by three. The PCI clock is output
through the PCLK pin. Externally this PCI clock drives a low skew clock driver which in turn
supplies multiple copies of the PCI clock to the PCI bus. One of the outputs of the external
clock driver is fed back into the PXB. A PLL in the PXB forces the external PCI clock to phase
lock to the internal PCI clock tree.
Intel® 450NX PCIset
11-1