450NX Datasheet, PDF (96/248 Pages) Intel Corporation – Intel 450NX PCIset

6. Memory Subsystem
interleave) that may be expanded beyond the first bank must therefore be designed using two
MUXs.
Table 6-2 gives a summary of the characteristics of memory configurations supported by the
Intel 450NX PCIset for 4-way interleaved memory cards.
Table 6-2: Minimum and Maximum Memory Size Per Card
DRAM
Technology &
Config.
DIMM
Size
Addressing
Mode
Size
row/col
Memory Size for
4-way Interleave
Min
(DIMMs)
Max
(DIMMs)
Max
(Double-
high
DIMMs)
16M 2M x 8 2M x 72 Asymmetric
4M x 4
4M x72 Symmetric
Asymmetric
64M 8M x 8 8M x 72 Asymmetric
16M x 4 16M x 72 Symmetric
Asymmetric
11 10
11 11
12 10
12 11
12 12
13 11
64 MB
128 MB
256 MB
512 MB
256 MB
512 MB
1 GB
2 GB
512 MB
1 GB
2 GB
4 GB
6.1.2.2
Address Bit Permuting Rules and Limitations
The Intel 450NX PCIset supports permuting of cache lines across two or four populated
banks. For a complete description of the operation of Address Bit Permuting (ABP) see Section
6.1.3.
The following rules and limitations are required for ABP to operate properly.
• All banks must be in 4:1 interleave mode.
• There must be a power of two number of banks populated.
• All banks within an ABP group (2 banks in 2 bank permuting and 4 banks in 4 bank
permuting) must be the same size.
• All populated rows must be adjacent and start at bank 0.
• Both cards in a system must be configured to allow equivilent ABP settings (i.e., Card 0
and Card 1 must both be configured according to the above rules for the current setting of
the ABP enable.)
6.1.2.3
Card to Card (C2C) Interleaving Rules and limitations
Card to Card Interleaving is described in detail in Section 6.1.4. All of the ABP rules defined
above apply to C2C interleaving, plus the following rules:
• The memory cards must be identically populated with memory DIMMs of the same size
and type.
• The DBC registers must be programmed in the alternate C2C order as defined in the C2C
functional description in Section 6.1.4.
6-4
Intel® 450NX PCIset