450NX Datasheet, PDF (125/248 Pages) Intel Corporation – Intel 450NX PCIset

Electrical Characteristics ₁₂
12.1 Signal Specifications
12.1.1 Unused Pins
For reliable operation, always connect unused inputs to an appropriate signal level. Unused
AGTL+ inputs should be connected to V_TT. Unused active low 3.3 V-tolerant inputs should be
connected to 3.3 V. Unused active high inputs should be connected to ground (V_SS). When
tying bidirectional signals to power or ground, a resistor must be used. When tying any signal
to power or ground, a resistor will also allow for fully testing the processor and PCIset after
board assembly. It is suggested that ~10KΩ resistors be used for pull-ups and ~1K Ω resistors
be used as pull-downs.
12.1.2 Signal Groups
In order to simplify the following discussion, signals have been combined into groups of like
characteristics (see below). Refer to Chapter 2 for a description of the signals and their
functions.
Table 12-1: Signal Groups MIOC
Pin Group
Signals
Notes
AGTL+ Input
AGTL+ Output
AGTL+ I/O
CMOS 14 mA 2.5 V Open Drain Output
(3.3 V Tolerant)
CMOS Input 3.3 V
LOCK#, PHIT(a,b)#, RCMPLT(a,b)#, RHIT(a,b)#,
X(0,1)RSTFB#, X(0,1)XRTS#, X(0,1)XSTBN#,
X(0,1)XSTBP#, HIT#, HITM#
BR[0]#, BANK[2:0]#, BREQ[0]#, CARD[1:0]#,
CMND[1:0]#, CSTB#, DOFF[1:0]#, DSEL[1:0]#,
DVALID(a,b)#, MA[13:0]#, MRESET#, ROW#,
X(0,1)BLK#, X(0,1)HRTS#, X(0,1)HSTBN#,
X(0,1)HSTBP#, X(0,1)RST#, X(0,1)RSTB#, WDEVT#
A[35:3]#, ADS#, AERR#, AP[1:0]#, BERR#, BINIT#,
BNR#, BPRI#, D[63:0]#, DBSY#, DCMPLT(a,b)#, DE-
FER#, DEP[7:0]#, DRDY#, DSTBN[3:0]#, DST-
BP[3:0]#, MD[71:0]#, REQ[4:0]#, RESET#, RP#,
RS[2:0]#, RSP#, TRDY#, X(0,1)ADS#, X(0,1)BE[1:0]#,
X(0,1)D[15:0]#, X(0,1)PAR#
INIT#, TDO
IOGNT#, TPCTL[1:0], PWRGD,
Intel® 450NX PCIset
12-1