450NX Datasheet, PDF (23/248 Pages) Intel Corporation – Intel 450NX PCIset

2.4 PCI Interface
the compatibility PCI bus). While in external arbitration mode, only one pair (#0) are used,
and have different meanings.
Each signal name includes a “p”, indicating the PCI bus port; p = A or B.
PpXARB#
External Arbitration Mode
PCI I
A strapping pin, sampled at the trailing edge of reset. If asserted, the PCI bus
is controlled using an external arbiter. If deasserted, the PCI bus is controlled
using the PXB’s internal arbiter. An internal pull-up insures that the pin
appears deasserted if left unconnected.
Internal Arbitration Mode (per PCI bus, p=A,B)
PpREQ[5:0]# PCI Bus Request
PCI I
Six independent PCI bus request signals used by the internal PCI arbiter for
PCI initiator arbitration. Unused signals should be strapped inactive.
PpGNT[5:0]#
PCI Grant
PCI O
Six independent PCI bus grant signals used by the internal PCI arbiter for PCI
initiator arbitration.
External Arbitration Mode (per PCI bus, p=A,B)
When operating in external arbitration mode, REQ[5:1]# and GNT[5:1]# signals are not used.
The REQ[0]# signal is redefined as HGNT#, and the GNT[0]# signal is redefined as HREQ#.
PpHREQ#
Host Request
PCI O
Generated by the PXB to the external PCI arbiter to request control of the PCI
bus to perform a Host-PCI access.
PpHGNT#
Host Grant
PCI I
Generated by the external PCI arbiter to grant the PCI bus to the PXB to
perform a Host-PCI transfer.
2.4.4
PIIX4E Interface
The compatibility PCI bus (PCI Bus 0A) supports a PIIX4E south bridge, and requires several
additional handshake signals, provided by the PXB. They are active only for Bus 0A.
NOTE
These signals, and the associated PHOLDA# and WSC# protocols, cannot be used with the PXB in
external arbiter mode.
PHOLD#
PHLDA#
PCI Hold
This signal is the PIIX4E’s request for the PCI bus.
PCI I
PCI Hold Acknowledge
PCI O
This signal is driven by the PXB to grant PCI bus ownership to the PIIX4E.
Intel® 450NX PCIset
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