450NX Datasheet, PDF (61/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
5:0 Outbound Read Data Buffer Capacity.
This field specifies the total number of data buffers, per PXB/PCI port, available in
the PXB for use by outbound read transactions, in increments of 32 bytes.
MIOC maximum: 16
Minimum allowed: 2
Default= 2
3.3.43 TOM: Top of Memory
Address Offset: 50-52h
Default Value: 000FFFh
Size:
24 bits
Attribute: Read/Write
Bits Description
23:0 Memory Address Ceiling.
Represents bits A[43:20] of the highest physical address to be directed toward this
node’s DRAM. The lower A[19:0] bits of this address are FFFFFh.
Default=000FFFh (4 GB-1).
3.3.44 VID: Vendor Identification Register
Address Offset: 00 - 01h
Default Value: 8086h
Size:
16 bits
Attributes: Read Only
Bits Description
15:0 Vendor Identification Number.
This is a 16-bit value assigned to Intel. Intel VID = 8086h.
3.4
PXB Configuration Space
Each PXB supports two independent PCI buses (Bus “A” and Bus “B”), which can be
configured independently. Each PCI bus therefore has its own configuration space. Both
configuration spaces are identical. When operating the PXB in 64-bit Bus Mode, only the A-
side configuration space is used. The B-side configuration space is not accessible while in 64-
bit mode.
Table 3-4 illustrates the PXB/PCI Bus Configuration Space Map.
Intel® 450NX PCIset
3-29