450NX Datasheet, PDF (78/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
and the Top of Memory (TOM); however, the base address must be aligned on the
next highest power-of-2 natural boundary given the chosen size. Incorrect alignment
results in indeterminate operation.
Default: 000Ah (representing a base address of A0000h)
3.4.30 TCAP: Target Capacity
Address Offset: C0-C2h
Default Value: 041082h
Size:
24 bits
Attribute: Read/Write
This register is programmed with the maximum number of transactions and data bytes that
the receiving MIOC can accept from this PXB/PCI port for inbound transactions. The MIOC
space has a set of four similar TCAP registers, one per PXB/PCI bus, that is programmed with
the transaction and data limits for outbound transactions.
If the PXB is in 32-bit bus mode, divide the MIOC BUFSIZ limits in half. If the PXB is in 64-bit
bus mode, the full MIOC BUFSIZ limits can be used, except in either case, the PXB’s
maximum values (shown below) cannot be exceeded.
Bits Description
23:18
Inbound Write Transaction Capacity.
This field specifies the total number of inbound write transactions that can be
forwarded and enqueued in the MIOC from this PXB/PCI port.
32-bit Bus PXB maximum: 6
Minimum allowed: 1
Default= 1
64-bit Bus PXB maximum: 12 Minimum allowed: 1
Default= 1
17:12
Inbound Read Transaction Capacity.
This field specifies the total number of inbound read transactions that can be
forwarded and enqueued in the MIOC from this PXB/PCI port.
32-bit Bus PXB maximum: 2
Minimum allowed: 1
Default= 1
64-bit Bus PXB maximum: 2
Minimum allowed: 1
Default= 1
11:6 Inbound Write Data Buffer Capacity.
This field specifies the total number of data buffers available in the MIOC for use by
inbound write transactions from this PXB/PCI port, in increments of 32 bytes.
32-bit Bus PXB maximum: 6
Minimum allowed: 2
Default= 2
64-bit Bus PXB maximum: 12 Minimum allowed: 2
Default= 2
5:0 Inbound Read Data Buffer Capacity.
This field specifies the total number of data buffers available in the MIOC for use by
inbound read transactions from this PXB/PCI port, in increments of 32 bytes.
32-bit Bus PXB maximum: 8
Minimum allowed: 2
Default= 2
64-bit Bus PXB maximum: 16 Minimum allowed: 2
Default= 2
3.4.31 TMODE: Timer Mode
Address Offset: C4h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
3-46
Intel® 450NX PCIset