450NX Datasheet, PDF (38/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
5
Live Port #1 Flag.
If set, the port is "live".
Default=0.
4
Live Port #0 Flag.
If set, the port is "live."
Default=1.
3:2 reserved
1
Test Port #1 Enable.
Setting this enable triggers the check connection protocol for port 1.
Default=0.
0
Test Port #0 Enable.
Setting this enable triggers the check connection protocol for port 0.
Default=0.
NOTE
Setting both Test Port #1 Enable and Test Port #0 Enable simultaneously is prohibited, and will have
unpredictable results, up to and including system hangs requiring a full system reset. Inactive PXBs
should be disabled by writing the corresponding Reset Expander Port bit in the RC register. Transactions
sent to inactive PXBs can result in system hangs.
3.3.4
CLASS: Class Code Register
Address Offset: 09 - 0Bh
Default Value: 060000h
Size:
24 bits
Attribute: Read Only
Bits Description
23:16 Base Class
For the MIOC, this field is hardwired to 06h.
15:8 Sub-Class
For the MIOC, this field is hardwired to 00h.
7:0 Register-Level Programming Interface
For the MIOC this field is hardwired to 00h.
3.3.5
CONFIG: Software-Defined Configuration Register
Address Offset: 40-41h
Default Value: 1000h
Size:
16 bits
Attribute: Read/Write
Bits Description
15:13 reserved (0)
3-6
Intel® 450NX PCIset