450NX Datasheet, PDF (40/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
1:0 Memory Address Bit Permuting.
The MIOC supports cache-line permuting across banks. This field controls the type of
permuting used, as follows:
00b No permuting.
01b 2-way Permuting.
10b 4-way Permuting.
11b reserved
Default=0.
3.3.6
CVCR: Configuration Values Captured on Reset
Address Offset: 4E-4Fh
Default Value: 0000h
Size:
16 bits
Attribute: Read-Only
This register captures the configuration values driven on A#[15:0] at the trailing edge of
RESET#. This allows an external device to override the default values provided by the MIOC
via its CVDR register.
Bits Description
15:13 reserved (0)
12:11 APIC Cluster ID.
Captured from A#[12:11]. Represents the APIC Cluster identifier.
10
Enable BINIT# Input.
Captured from A#[10]. If set, the MIOC will observe the assertion of the BINIT# input.
Further details on BINIT# processing may be found in the ERRCMD register.
9
Enable BERR# Input.
Captured from A#[9]. If set, the MIOC will observe the assertion of the BERR# input.
Further details on BERR# processing may be found in the ERRCMD register.
8
Enable AERR# Input.
Captured from A#[8]. If set, the MIOC will observe the assertion of the AERR# input.
Further details on AERR# processing may be found in the ERRCMD register. If this
enable is asserted, then the BINIT# Driver Enable in the ERRCMD register must also
be asserted.
7
In-Order Queue Depth 1.
Captured from A#[7]. If set, the MIOC will limit its In-Order Queue Depth to 1 (no
pipelining support), instead of the usual 8.
6
1M Power-on Reset Vector.
Captured from A#[6]. This bit has no meaning for the MIOC. If set, all Pentium^® II
Xeon™ processors on the system bus will use the 1MB-1 (000FFFFFh) reset vector,
instead of their usual 4 GB-1 (FFFFFFFFh) vector.
5
Enable FRC Mode.
Captured from A#[5]. This bit has no meaning for the MIOC. If set, all Pentium II
Xeon processors on the system bus will enter FRC-enabled mode.
4:0 reserved (0)
3-8
Intel® 450NX PCIset