450NX Datasheet, PDF (139/248 Pages) Intel Corporation – Intel 450NX PCIset

12.4 AC Specifications
Notes:
1.
2.
3.
4.
5.
6.
7.
5 V-tolerant.
3.3 V-tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
Min timings are measured with 0pF load, Max timings are measured with 50pF load.
Min and Max timings are measured with 0pF load.
TRST# requires a pulse width of 40 ns.
This signal has an asynchronous assertion and a synchronous deassertion.
This input is asynchronous.
PCI Bus Signal Waveforms: All PCI Bus signals are referenced to the PCLK Rising edge. For
more information on the PCI Bus signals and waveforms, please refer to the PCI Specification.
Table 12-14: Intel^® 450NX PCIset RCG AC Specifications
Vcc₃ = 3.3 V (5%, T_CASE = 0 to 85 ^oC)
Symbol Parameter
Setup
Min
Memory Subsystem/External
Interface
T50
BANK[2:0]#, CARD#,
2.80
CMND[1:0]#, CSTB#,
MA[13:0]#, ROW#
T51
GRCMPLT#
2.80
T52
PHIT#, RCMPLT#, RHIT#
Memory Subsystem/Internal
Interface
T52
AVWP#, LRD#, WDME#, LD-
STB#
T53
CAS(A,B,C,D)(a,b,c,d)[1:0]#
T54
ADDR(A,B,C,D)[13:0]#
T53
RAS(A,B,C,D)(a,b,c,d)[1:0]#
T53
WE(A,B,C,D)(a,b)#
Other
T50
MRESET#
2.8
T26
TRST#
T27
TMS
5.0
T27
TDI
5.0
T28
TDO
T29
TDO on/off delay
Hold
Min
0.0
0.0
0.0
14.0
14.0
Delay
Min
-0.15
-0.15
-0.15
0.0
1.0
0.0
0.0
1.0
Delay
Max
Unit Notes
ns
2.65
ns
6
2.65
ns
6
2.65
ns
6
3.5
ns
3
5.5
ns
3
3.5
ns
3
3.5
ns
3
ns
5
ns
4, 7
ns
2
ns
2
10.0
ns
2, 3
25.0
ns
2, 3
Notes:
1.
2.
3.
4.
5.
6.
7.
The power supply must wait until all voltages are stable for at least 1ms, and then assert the PWRGD
signal.
3.3- tolerant signals. Inputs are referenced to TCK rising, outputs are referenced to TCK falling.
Min and Max timings are measured with 0pF load.
TRST# requires a pulse width of 40 ns.
Max delay timing requirement from MIOC to RCGs and MUXs is two clock cycles. Asynchronous
assertion and synchronous deassertion.
Min and Max timings are measured with 0pF and 25Ω to Vtt (1.5 V).
This input is asynchronous.
Intel® 450NX PCIset
12-15