450NX Datasheet, PDF (66/248 Pages) Intel Corporation – Intel 450NX PCIset

3. Register Descriptions
Bits Description
15:0 Device Identification Number.
The value 84CBh indicates the Intel^® 450NX PCIset PXB.
3.4.6
ERRCMD: Error Command Register
Address Offset: 46h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write
This register provides extended control over the assertion of SERR# beyond the basic controls
specified in the PCI-standard PCICMD register.
Bits Description
7
reserved
6
Assert SERR# on Observed Parity Error.
If set, the PXB asserts SERR# if PERR# is observed asserted, and the PXB was not the
asserting agent.
5
Assert SERR# on Received Data with Parity Error.
If set, the PXB asserts SERR# upon receiving PCI data with a parity error. This occurs
regardless of whether PXB asserts it's PERR# pin.
4
Assert SERR# on Address Parity Error.
If set, the PXB asserts SERR# on detecting a PCI address parity error.
3
Assert PERR# on Data Parity Error.
If set, and the PERRE bit is set in the PCICMD register, the PXB asserts PERR# upon
receiving PCI data with parity errors.
2
Assert SERR# On Inbound Delayed Read Time-out.
Each inbound read request that is accepted and serviced as a delayed read will start a
watchdog timer (2¹⁵ cycles). If this enable is set, the PXB will assert SERR# if the data
has been returned and the timer expires before the requesting master initiates its
repeat request. Default=0.
1
Assert SERR# on Expander Bus Parity Error.
If set, the PXB asserts SERR# upon detecting a parity error on packets arriving from
the Expander bus. (Note that SERR# will be asserted on both PCI buses).
0
Return Hard Fail Upon Generating Master Abort.
If set, the PXB will return a Hard Fail response through the MIOC to the system bus
after generating a master abort time-out for an outbound transaction placed on the
PCI bus. If cleared, the PXB will return a normal response (with data of all 1’s for a
read). In either case, an error flag is set in the PCISTS register. Default=0.
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Intel® 450NX PCIset