450NX Datasheet, PDF (102/248 Pages) Intel Corporation – Intel 450NX PCIset

7. Transaction Summary
Table 7-3: TPCTL[1:0] Operations
TPCTL
[1:0]
Action
00 Accept. The MIOC accepts the request, and provides the normal response.
The third-party agent is not involved in the transaction.
01 Hard Fail. Not supported by the Intel^® 450NX PCIset.
10 Retry. The MIOC will generate a retry response. The access will be retried by
the requesting agent.
11 Defer. The MIOC will issue a defer response, and the third-party agent will
complete the transaction at a later time using a deferred reply.
7.2 Outbound Transactions
7.2.1
Supported Outbound Accesses
The PXB translates valid system bus commands into PCI bus requests. For all Host-PCI
transactions the PXB is a non-caching agent since the Intel 450NX PCIset does not support
cacheability on PCI. However, the PXB must respond appropriately to the system bus
commands that are cache oriented.
7.2.2
Outbound Locked Transactions
The Intel 450NX PCIset supports memory-mapped outbound locked operations. I/O-
mapped outbound locked transactions are not supported. Further, a locked transaction
cannot be initiated with a zero-length read. These restrictions are consistent with the
transactions supported by the processor.
7.2.3
Outbound Write Combining
The Intel 450NX PCIset provides its own write combining for Host-PCI write transactions. If
enabled, and multiple Host-PCI writes target sequential locations in the PCI space, the data is
combined and sent to the PCI bus as a single write burst. This holds true for all memory
attributes, not just WC. There is no corresponding write-combining for the Host-DRAM
path.
7.2.4
Third-Party Intervention on Outbounds
The use of the third-party control signals (TPCTL) is not supported for outbound transactions
(Host-PCI). Assertion of the TPCTL signals during an outbound transaction will have
7-4
Intel® 450NX PCIset