450NX Datasheet, PDF (67/248 Pages) Intel Corporation – Intel 450NX PCIset

3.4 PXB Configuration Space
3.4.7
ERRSTS: Error Status Register
Address Offset: 44h
Default Value: 00h
Size:
8 bits
Attribute: Read/Write Clear, Sticky
This register records error conditions detected from the PCI bus (not already covered in
PCISTS), from the Expander bus, and performance monitoring events. Bits remain set until
explicitly cleared by software writing a 1 to the bit.
Bits Description
7
reserved(0)
6
Parity Error observed on PCI Data.
This flag is set if the PXB detects the PERR# input asserted, and the PXB was not the
asserting agent. This flag may be configured to assert SERR# or PERR# in the
ERRCMD register.
5
Parity Error on Received PCI Data.
This flag is set if the PXB detects a parity error on data being read from the PCI bus.
This flag may be configured to assert SERR# or PERR# in the ERRCMD register.
4
Parity Error on PCI Address.
This flag is set if the PXB detects a parity error on the PCI address. This flag may be
configured to assert SERR# in the ERRCMD register.
3
Inbound Delayed Read Time-out Flag.
Each inbound read request that is accepted and serviced as a delayed read will initiate
a watchdog timer (2¹⁵ cycles). If the data has been returned and the timer expires
before the requesting master initiates its repeat request, this flag will be set. This flag
may be configured to assert SERR# or PERR# in the ERRCMD register.
2
Expander Bus Parity Error Flag.
This flag is set when Expander bus reports a parity error on packets received from the
MIOC. This flag is set in both PCI configuration spaces. This flag may be configured
to assert SERR# or PERR# in the ERRCMD register.
1
Performance Monitor #1 Event Flag.
This flag is set when the Performance Monitor #1 requests that an interrupt request be
asserted. The PME and PMR registers describe the conditions that can cause this to
occur. While this bit is set, the INT(A,B)RQ# line will be asserted.
0
Performance Monitor #0 Event Flag.
This flag is set when the Performance Monitor #0 requests that an interrupt request be
asserted. The PME and PMR registers describe the conditions that can cause this to
occur. While this bit is set, the INT(A,B)RQ# line will be asserted.
Intel® 450NX PCIset
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