450NX Datasheet, PDF (109/248 Pages) Intel Corporation – Intel 450NX PCIset

Data Integrity & Error Handling ₉
This chapter describes the data integrity support and general error detection and reporting
mechanisms used in the Intel^® 450NX PCIset.
9.1
DRAM Integrity
Both the system data bus and the Intel^® 450NX PCIset’s memory subsystem use a common
Error Correcting Code which provides SEC/DED/NED coverage. The ECC used is capable of
correcting single-bit errors and detecting 100% of double-bit errors over one code word.
9.1.1
ECC Generation
When enabled, the DRAM ECC mechanism allows automatic generation of an 8-bit
protection code for the 64-bit (Qword) of data during DRAM write operations. Note that
when ECC is intended to be enabled, the whole DRAM array must be first initialized by doing
writes before the DRAM read operations can be performed. This will establish the correlation
between 64-bit data and associated 8-bit ECC code which does not exist after power-on. This
function is not provided by hardware.
9.1.2
ECC Checking and Correction
During DRAM read operations, a full Qword of data (8 bytes) is always transferred from the
DRAM to the MIOC regardless of the size of the originally requested data. Both 64-bit data
and 8-bit ECC code are transferred simultaneously from the DRAM to the MIOC. The ECC
checking logic in the MIOC uses the received 72 bit Data + ECC to generate the check
syndrome. If a single-bit error is detected the ECC logic corrects the identified incorrect data
bit.
9.1.3
ECC Error Reporting
When ECC checking is enabled, single-bit and multiple-bit errors detected by the ECC logic
are logged in the MIOC. The first two errors detected on reads-from-memory are logged, as
are the first two errors detected on data received from the system bus.
For memory errors, the error type (single-bit or multi-bit), syndrome, chunk and effective
address are logged. The first two memory errors (single-bit or multi-bit) will be logged in the
Intel® 450NX PCIset
9-1