450NX Datasheet, PDF (35/248 Pages) Intel Corporation – Intel 450NX PCIset

3.3 MIOC Configuration Space
3.3 MIOC Configuration Space
Table 3-1: MIOC Configuration Space ¹
DID
VID
00h
DBC 01
DBC 00
80h
04h
DBC 03
DBC 02
84h
CLASS
RID 08h
DBC 05
DBC 04
88h
HDR
0Ch
DBC 07
DBC 06
8Ch
10h
DBC 09
DBC 08
90h
14h
DBC 11
DBC 10
94h
18h
DBC 13
DBC 12
98h
1Ch
DBC 15
DBC 14
9Ch
RCGP
Reserved
A0h
24h
REFRESH
A4h
28h
MEA1 MEA0 A8h
2Ch
ACh
30h
MEL1
MEL0
B0h
34h
HEL1
HEL0
B4h
38h
ECCMSK ECCCMD B8h
3Ch
BCh
CHKCON RC
CONFIG
40h
ROUTE0
TCAP0
C0h
ERRCMD
ERRSTS
44h
TCAP1
C4h
BUFSIZ
48h
ROUTE1
TCAP2
C8h
CVCR
CVDR
4Ch
TCAP3
CCh
TOM
50h
BUSNO1 SUBB0 SUBA0 BUSNO0 D0h
LXGT
LXGB
54h
DEVMAP
SUBB1 SUBA1 D4h
HXGB
58h
PMD0
D8h
HXGT
5Ch
PMR0 PMD0 DCh
MAR2 MAR1 MAR0 GAPEN 60h
PMD1
E0h
MAR6 MAR5 MAR4 MAR3 64h
PMR1 PMD1 E4h
IOAR
IOABASE
68h
PME1
PME0
E8h
SMRAM
6Ch
ECh
MMBASE
70h
F0h
MMR1
MMR0
74h
F4h
MMR3
MMR2
78h
F8h
IOR
ISA 7Ch
FCh
1. The first 64 bytes are predefined in the PCI Specification. All other locations are defined specifically for the
component of interest.
Intel® 450NX PCIset
3-3